e2771545f4
The codec clock on sun4i, sun5i and sun7i is a simple gate with PLL2 as parent. Add a driver for such a clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* Copyright 2013 Emilio López
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*
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* Emilio López <emilio@elopez.com.ar>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define SUN4I_CODEC_GATE 31
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static void __init sun4i_codec_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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const char *clk_name = node->name, *parent_name;
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void __iomem *reg;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent_name = of_clk_get_parent_name(node, 0);
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clk = clk_register_gate(NULL, clk_name, parent_name,
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CLK_SET_RATE_PARENT, reg,
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SUN4I_CODEC_GATE, 0, NULL);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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CLK_OF_DECLARE(sun4i_codec, "allwinner,sun4i-a10-codec-clk",
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sun4i_codec_clk_setup);
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