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Maciej W. Rozycki 8ff374b9c2 MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks 
Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout.
The change does not touch places that use shifted or partial masks.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5838/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 		2013-09-18 20:25:19 +02:00
..
common MIPS: Netlogic: XLP2XX CPU and PIC frequency 2013-09-03 23:22:19 +02:00
dts MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards 2013-09-03 23:22:20 +02:00
xlp MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards 2013-09-03 23:22:20 +02:00
xlr MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks 2013-09-18 20:25:19 +02:00
Kconfig MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards 2013-09-03 23:22:20 +02:00
Makefile MIPS: Netlogic: Add support for built in DTB 2012-08-22 23:46:37 +02:00
Platform MIPS: Whitespace cleanup. 2013-02-01 10:00:22 +01:00