c8a8309049
The Allwinner H6 SoC has two pin controllers, one main controller (called CPUX-PORT in user manual) and one controller in CPUs power domain (called CPUS-PORT in user manual). This commit introduces support for the main pin controller on H6. The pin bank A and B are not wired out and hidden from the SoC's documents, however it's shown that the "ATE" (an AC200 chip co-packaged with the H6 die) is connected to the main SoC die via these pin banks. The information about these banks is just copied from the BSP pinctrl driver, but re-formatted to fit the mainline pinctrl driver format. The GPIO functions are dropped, as they're impossible to use -- except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pinctrl-sun4i-a10.c | ||
| pinctrl-sun5i.c | ||
| pinctrl-sun6i-a31-r.c | ||
| pinctrl-sun6i-a31.c | ||
| pinctrl-sun8i-a23-r.c | ||
| pinctrl-sun8i-a23.c | ||
| pinctrl-sun8i-a33.c | ||
| pinctrl-sun8i-a83t-r.c | ||
| pinctrl-sun8i-a83t.c | ||
| pinctrl-sun8i-h3-r.c | ||
| pinctrl-sun8i-h3.c | ||
| pinctrl-sun8i-v3s.c | ||
| pinctrl-sun9i-a80-r.c | ||
| pinctrl-sun9i-a80.c | ||
| pinctrl-sun50i-a64-r.c | ||
| pinctrl-sun50i-a64.c | ||
| pinctrl-sun50i-h5.c | ||
| pinctrl-sun50i-h6.c | ||
| pinctrl-sunxi.c | ||
| pinctrl-sunxi.h | ||