774 lines
21 KiB
C
774 lines
21 KiB
C
/*
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* Intel I/OAT DMA Linux driver
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* Copyright(c) 2004 - 2009 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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/*
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* This driver supports an Intel I/OAT DMA engine (versions >= 2), which
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* does asynchronous data movement and checksumming operations.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/workqueue.h>
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#include <linux/i7300_idle.h>
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#include "dma.h"
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#include "dma_v2.h"
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#include "registers.h"
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#include "hw.h"
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static int ioat_ring_alloc_order = 8;
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module_param(ioat_ring_alloc_order, int, 0644);
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MODULE_PARM_DESC(ioat_ring_alloc_order,
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"ioat2+: allocate 2^n descriptors per channel (default: n=8)");
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static void __ioat2_issue_pending(struct ioat2_dma_chan *ioat)
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{
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void * __iomem reg_base = ioat->base.reg_base;
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ioat->pending = 0;
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ioat->dmacount += ioat2_ring_pending(ioat);
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ioat->issued = ioat->head;
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/* make descriptor updates globally visible before notifying channel */
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wmb();
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writew(ioat->dmacount, reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
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dev_dbg(to_dev(&ioat->base),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
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}
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static void ioat2_issue_pending(struct dma_chan *chan)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(chan);
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spin_lock_bh(&ioat->ring_lock);
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if (ioat->pending == 1)
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__ioat2_issue_pending(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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}
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/**
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* ioat2_update_pending - log pending descriptors
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* @ioat: ioat2+ channel
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*
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* set pending to '1' unless pending is already set to '2', pending == 2
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* indicates that submission is temporarily blocked due to an in-flight
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* reset. If we are already above the ioat_pending_level threshold then
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* just issue pending.
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*
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* called with ring_lock held
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*/
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static void ioat2_update_pending(struct ioat2_dma_chan *ioat)
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{
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if (unlikely(ioat->pending == 2))
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return;
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else if (ioat2_ring_pending(ioat) > ioat_pending_level)
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__ioat2_issue_pending(ioat);
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else
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ioat->pending = 1;
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}
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static void __ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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{
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void __iomem *reg_base = ioat->base.reg_base;
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struct ioat_ring_ent *desc;
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struct ioat_dma_descriptor *hw;
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int idx;
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if (ioat2_ring_space(ioat) < 1) {
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dev_err(to_dev(&ioat->base),
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"Unable to start null desc - ring full\n");
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return;
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}
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dev_dbg(to_dev(&ioat->base), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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idx = ioat2_desc_alloc(ioat, 1);
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desc = ioat2_get_ring_ent(ioat, idx);
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hw = desc->hw;
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hw->ctl = 0;
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hw->ctl_f.null = 1;
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hw->ctl_f.int_en = 1;
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hw->ctl_f.compl_write = 1;
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/* set size to non-zero value (channel returns error when size is 0) */
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hw->size = NULL_DESC_BUFFER_SIZE;
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hw->src_addr = 0;
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hw->dst_addr = 0;
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async_tx_ack(&desc->txd);
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writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
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reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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writel(((u64) desc->txd.phys) >> 32,
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reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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dump_desc_dbg(ioat, desc);
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__ioat2_issue_pending(ioat);
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}
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static void ioat2_start_null_desc(struct ioat2_dma_chan *ioat)
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{
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spin_lock_bh(&ioat->ring_lock);
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__ioat2_start_null_desc(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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}
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static void ioat2_cleanup(struct ioat2_dma_chan *ioat);
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/**
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* ioat2_reset_part2 - reinit the channel after a reset
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*/
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static void ioat2_reset_part2(struct work_struct *work)
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{
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struct ioat_chan_common *chan;
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struct ioat2_dma_chan *ioat;
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chan = container_of(work, struct ioat_chan_common, work.work);
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ioat = container_of(chan, struct ioat2_dma_chan, base);
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/* ensure that ->tail points to the stalled descriptor
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* (ioat->pending is set to 2 at this point so no new
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* descriptors will be issued while we perform this cleanup)
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*/
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ioat2_cleanup(ioat);
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spin_lock_bh(&chan->cleanup_lock);
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spin_lock_bh(&ioat->ring_lock);
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/* set the tail to be re-issued */
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ioat->issued = ioat->tail;
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ioat->dmacount = 0;
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dev_dbg(to_dev(&ioat->base),
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"%s: head: %#x tail: %#x issued: %#x count: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued, ioat->dmacount);
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if (ioat2_ring_pending(ioat)) {
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struct ioat_ring_ent *desc;
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desc = ioat2_get_ring_ent(ioat, ioat->tail);
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writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
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chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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writel(((u64) desc->txd.phys) >> 32,
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chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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__ioat2_issue_pending(ioat);
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} else
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__ioat2_start_null_desc(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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spin_unlock_bh(&chan->cleanup_lock);
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dev_info(to_dev(chan),
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"chan%d reset - %d descs waiting, %d total desc\n",
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chan_num(chan), ioat->dmacount, 1 << ioat->alloc_order);
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}
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/**
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* ioat2_reset_channel - restart a channel
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* @ioat: IOAT DMA channel handle
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*/
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static void ioat2_reset_channel(struct ioat2_dma_chan *ioat)
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{
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u32 chansts, chanerr;
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struct ioat_chan_common *chan = &ioat->base;
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u16 active;
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spin_lock_bh(&ioat->ring_lock);
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active = ioat2_ring_active(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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if (!active)
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return;
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS;
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if (chanerr) {
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dev_err(to_dev(chan),
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"chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
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chan_num(chan), chansts, chanerr);
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writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
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}
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spin_lock_bh(&ioat->ring_lock);
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ioat->pending = 2;
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writeb(IOAT_CHANCMD_RESET,
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chan->reg_base
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+ IOAT_CHANCMD_OFFSET(chan->device->version));
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spin_unlock_bh(&ioat->ring_lock);
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schedule_delayed_work(&chan->work, RESET_DELAY);
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}
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/**
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* ioat2_chan_watchdog - watch for stuck channels
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*/
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static void ioat2_chan_watchdog(struct work_struct *work)
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{
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struct ioatdma_device *device =
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container_of(work, struct ioatdma_device, work.work);
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struct ioat2_dma_chan *ioat;
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struct ioat_chan_common *chan;
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u16 active;
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int i;
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dev_dbg(&device->pdev->dev, "%s\n", __func__);
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for (i = 0; i < device->common.chancnt; i++) {
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chan = ioat_chan_by_index(device, i);
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ioat = container_of(chan, struct ioat2_dma_chan, base);
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/*
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* for version 2.0 if there are descriptors yet to be processed
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* and the last completed hasn't changed since the last watchdog
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* if they haven't hit the pending level
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* issue the pending to push them through
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* else
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* try resetting the channel
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*/
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spin_lock_bh(&ioat->ring_lock);
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active = ioat2_ring_active(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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if (active &&
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chan->last_completion &&
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chan->last_completion == chan->watchdog_completion) {
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if (ioat->pending == 1)
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ioat2_issue_pending(&chan->common);
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else {
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ioat2_reset_channel(ioat);
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chan->watchdog_completion = 0;
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}
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} else {
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chan->last_compl_desc_addr_hw = 0;
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chan->watchdog_completion = chan->last_completion;
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}
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chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie;
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}
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schedule_delayed_work(&device->work, WATCHDOG_DELAY);
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}
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/**
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* ioat2_cleanup - clean finished descriptors (advance tail pointer)
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* @chan: ioat channel to be cleaned up
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*/
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static void ioat2_cleanup(struct ioat2_dma_chan *ioat)
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{
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struct ioat_chan_common *chan = &ioat->base;
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unsigned long phys_complete;
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struct ioat_ring_ent *desc;
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bool seen_current = false;
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u16 active;
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int i;
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struct dma_async_tx_descriptor *tx;
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prefetch(chan->completion);
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spin_lock_bh(&chan->cleanup_lock);
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phys_complete = ioat_get_current_completion(chan);
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if (phys_complete == chan->last_completion) {
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spin_unlock_bh(&chan->cleanup_lock);
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/*
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* perhaps we're stuck so hard that the watchdog can't go off?
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* try to catch it after WATCHDOG_DELAY seconds
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*/
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if (chan->device->version < IOAT_VER_3_0) {
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unsigned long tmo;
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tmo = chan->last_completion_time + HZ*WATCHDOG_DELAY;
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if (time_after(jiffies, tmo)) {
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ioat2_chan_watchdog(&(chan->device->work.work));
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chan->last_completion_time = jiffies;
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}
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}
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return;
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}
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chan->last_completion_time = jiffies;
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spin_lock_bh(&ioat->ring_lock);
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dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n",
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__func__, ioat->head, ioat->tail, ioat->issued);
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active = ioat2_ring_active(ioat);
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for (i = 0; i < active && !seen_current; i++) {
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prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1));
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desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
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tx = &desc->txd;
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dump_desc_dbg(ioat, desc);
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if (tx->cookie) {
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ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
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chan->completed_cookie = tx->cookie;
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tx->cookie = 0;
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if (tx->callback) {
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tx->callback(tx->callback_param);
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tx->callback = NULL;
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}
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}
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if (tx->phys == phys_complete)
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seen_current = true;
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}
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ioat->tail += i;
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BUG_ON(!seen_current); /* no active descs have written a completion? */
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spin_unlock_bh(&ioat->ring_lock);
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chan->last_completion = phys_complete;
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spin_unlock_bh(&chan->cleanup_lock);
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}
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static void ioat2_cleanup_tasklet(unsigned long data)
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{
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struct ioat2_dma_chan *ioat = (void *) data;
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ioat2_cleanup(ioat);
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writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
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}
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/**
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* ioat2_enumerate_channels - find and initialize the device's channels
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* @device: the device to be enumerated
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*/
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static int ioat2_enumerate_channels(struct ioatdma_device *device)
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{
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struct ioat2_dma_chan *ioat;
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struct device *dev = &device->pdev->dev;
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struct dma_device *dma = &device->common;
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u8 xfercap_log;
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int i;
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INIT_LIST_HEAD(&dma->channels);
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dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
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dma->chancnt &= 0x1f; /* bits [4:0] valid */
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if (dma->chancnt > ARRAY_SIZE(device->idx)) {
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dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
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dma->chancnt, ARRAY_SIZE(device->idx));
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dma->chancnt = ARRAY_SIZE(device->idx);
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}
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xfercap_log = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
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xfercap_log &= 0x1f; /* bits [4:0] valid */
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if (xfercap_log == 0)
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return 0;
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dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
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/* FIXME which i/oat version is i7300? */
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#ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL
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if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
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dma->chancnt--;
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#endif
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for (i = 0; i < dma->chancnt; i++) {
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ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
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if (!ioat)
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break;
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ioat_init_channel(device, &ioat->base, i,
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ioat2_reset_part2,
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ioat2_cleanup_tasklet,
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(unsigned long) ioat);
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ioat->xfercap_log = xfercap_log;
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spin_lock_init(&ioat->ring_lock);
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}
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dma->chancnt = i;
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return i;
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}
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static dma_cookie_t ioat2_tx_submit_unlock(struct dma_async_tx_descriptor *tx)
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{
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struct dma_chan *c = tx->chan;
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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dma_cookie_t cookie = c->cookie;
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cookie++;
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if (cookie < 0)
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cookie = 1;
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tx->cookie = cookie;
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c->cookie = cookie;
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dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
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ioat2_update_pending(ioat);
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spin_unlock_bh(&ioat->ring_lock);
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return cookie;
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}
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static struct ioat_ring_ent *ioat2_alloc_ring_ent(struct dma_chan *chan)
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{
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struct ioat_dma_descriptor *hw;
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struct ioat_ring_ent *desc;
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struct ioatdma_device *dma;
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dma_addr_t phys;
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dma = to_ioatdma_device(chan->device);
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hw = pci_pool_alloc(dma->dma_pool, GFP_KERNEL, &phys);
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if (!hw)
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return NULL;
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memset(hw, 0, sizeof(*hw));
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc) {
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pci_pool_free(dma->dma_pool, hw, phys);
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return NULL;
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}
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dma_async_tx_descriptor_init(&desc->txd, chan);
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desc->txd.tx_submit = ioat2_tx_submit_unlock;
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desc->hw = hw;
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desc->txd.phys = phys;
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return desc;
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}
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static void ioat2_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan)
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{
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struct ioatdma_device *dma;
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dma = to_ioatdma_device(chan->device);
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pci_pool_free(dma->dma_pool, desc->hw, desc->txd.phys);
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kfree(desc);
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}
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/* ioat2_alloc_chan_resources - allocate/initialize ioat2 descriptor ring
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* @chan: channel to be initialized
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*/
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static int ioat2_alloc_chan_resources(struct dma_chan *c)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_ring_ent **ring;
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u32 chanerr;
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int descs;
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int i;
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/* have we already been set up? */
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if (ioat->ring)
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return 1 << ioat->alloc_order;
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/* Setup register to interrupt and write completion status on error */
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writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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if (chanerr) {
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dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
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writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
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}
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/* allocate a completion writeback area */
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/* doing 2 32bit writes to mmio since 1 64b write doesn't work */
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chan->completion = pci_pool_alloc(chan->device->completion_pool,
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GFP_KERNEL, &chan->completion_dma);
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if (!chan->completion)
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return -ENOMEM;
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|
|
|
memset(chan->completion, 0, sizeof(*chan->completion));
|
|
writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
|
|
chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
|
|
writel(((u64) chan->completion_dma) >> 32,
|
|
chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
|
|
|
|
ioat->alloc_order = ioat_get_alloc_order();
|
|
descs = 1 << ioat->alloc_order;
|
|
|
|
/* allocate the array to hold the software ring */
|
|
ring = kcalloc(descs, sizeof(*ring), GFP_KERNEL);
|
|
if (!ring)
|
|
return -ENOMEM;
|
|
for (i = 0; i < descs; i++) {
|
|
ring[i] = ioat2_alloc_ring_ent(c);
|
|
if (!ring[i]) {
|
|
while (i--)
|
|
ioat2_free_ring_ent(ring[i], c);
|
|
kfree(ring);
|
|
return -ENOMEM;
|
|
}
|
|
set_desc_id(ring[i], i);
|
|
}
|
|
|
|
/* link descs */
|
|
for (i = 0; i < descs-1; i++) {
|
|
struct ioat_ring_ent *next = ring[i+1];
|
|
struct ioat_dma_descriptor *hw = ring[i]->hw;
|
|
|
|
hw->next = next->txd.phys;
|
|
}
|
|
ring[i]->hw->next = ring[0]->txd.phys;
|
|
|
|
spin_lock_bh(&ioat->ring_lock);
|
|
ioat->ring = ring;
|
|
ioat->head = 0;
|
|
ioat->issued = 0;
|
|
ioat->tail = 0;
|
|
ioat->pending = 0;
|
|
spin_unlock_bh(&ioat->ring_lock);
|
|
|
|
tasklet_enable(&chan->cleanup_task);
|
|
ioat2_start_null_desc(ioat);
|
|
|
|
return descs;
|
|
}
|
|
|
|
/**
|
|
* ioat2_alloc_and_lock - common descriptor alloc boilerplate for ioat2,3 ops
|
|
* @idx: gets starting descriptor index on successful allocation
|
|
* @ioat: ioat2,3 channel (ring) to operate on
|
|
* @num_descs: allocation length
|
|
*/
|
|
static int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs)
|
|
{
|
|
struct ioat_chan_common *chan = &ioat->base;
|
|
|
|
spin_lock_bh(&ioat->ring_lock);
|
|
if (unlikely(ioat2_ring_space(ioat) < num_descs)) {
|
|
if (printk_ratelimit())
|
|
dev_dbg(to_dev(chan),
|
|
"%s: ring full! num_descs: %d (%x:%x:%x)\n",
|
|
__func__, num_descs, ioat->head, ioat->tail,
|
|
ioat->issued);
|
|
spin_unlock_bh(&ioat->ring_lock);
|
|
|
|
/* do direct reclaim in the allocation failure case */
|
|
ioat2_cleanup(ioat);
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
dev_dbg(to_dev(chan), "%s: num_descs: %d (%x:%x:%x)\n",
|
|
__func__, num_descs, ioat->head, ioat->tail, ioat->issued);
|
|
|
|
*idx = ioat2_desc_alloc(ioat, num_descs);
|
|
return 0; /* with ioat->ring_lock held */
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *
|
|
ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
|
|
dma_addr_t dma_src, size_t len, unsigned long flags)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
struct ioat_dma_descriptor *hw;
|
|
struct ioat_ring_ent *desc;
|
|
dma_addr_t dst = dma_dest;
|
|
dma_addr_t src = dma_src;
|
|
size_t total_len = len;
|
|
int num_descs;
|
|
u16 idx;
|
|
int i;
|
|
|
|
num_descs = ioat2_xferlen_to_descs(ioat, len);
|
|
if (likely(num_descs) &&
|
|
ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0)
|
|
/* pass */;
|
|
else
|
|
return NULL;
|
|
for (i = 0; i < num_descs; i++) {
|
|
size_t copy = min_t(size_t, len, 1 << ioat->xfercap_log);
|
|
|
|
desc = ioat2_get_ring_ent(ioat, idx + i);
|
|
hw = desc->hw;
|
|
|
|
hw->size = copy;
|
|
hw->ctl = 0;
|
|
hw->src_addr = src;
|
|
hw->dst_addr = dst;
|
|
|
|
len -= copy;
|
|
dst += copy;
|
|
src += copy;
|
|
dump_desc_dbg(ioat, desc);
|
|
}
|
|
|
|
desc->txd.flags = flags;
|
|
desc->len = total_len;
|
|
hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
|
|
hw->ctl_f.compl_write = 1;
|
|
dump_desc_dbg(ioat, desc);
|
|
/* we leave the channel locked to ensure in order submission */
|
|
|
|
return &desc->txd;
|
|
}
|
|
|
|
/**
|
|
* ioat2_free_chan_resources - release all the descriptors
|
|
* @chan: the channel to be cleaned
|
|
*/
|
|
static void ioat2_free_chan_resources(struct dma_chan *c)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
struct ioat_chan_common *chan = &ioat->base;
|
|
struct ioatdma_device *ioatdma_device = chan->device;
|
|
struct ioat_ring_ent *desc;
|
|
const u16 total_descs = 1 << ioat->alloc_order;
|
|
int descs;
|
|
int i;
|
|
|
|
/* Before freeing channel resources first check
|
|
* if they have been previously allocated for this channel.
|
|
*/
|
|
if (!ioat->ring)
|
|
return;
|
|
|
|
tasklet_disable(&chan->cleanup_task);
|
|
ioat2_cleanup(ioat);
|
|
|
|
/* Delay 100ms after reset to allow internal DMA logic to quiesce
|
|
* before removing DMA descriptor resources.
|
|
*/
|
|
writeb(IOAT_CHANCMD_RESET,
|
|
chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
|
|
mdelay(100);
|
|
|
|
spin_lock_bh(&ioat->ring_lock);
|
|
descs = ioat2_ring_space(ioat);
|
|
dev_dbg(to_dev(chan), "freeing %d idle descriptors\n", descs);
|
|
for (i = 0; i < descs; i++) {
|
|
desc = ioat2_get_ring_ent(ioat, ioat->head + i);
|
|
ioat2_free_ring_ent(desc, c);
|
|
}
|
|
|
|
if (descs < total_descs)
|
|
dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
|
|
total_descs - descs);
|
|
|
|
for (i = 0; i < total_descs - descs; i++) {
|
|
desc = ioat2_get_ring_ent(ioat, ioat->tail + i);
|
|
dump_desc_dbg(ioat, desc);
|
|
ioat2_free_ring_ent(desc, c);
|
|
}
|
|
|
|
kfree(ioat->ring);
|
|
ioat->ring = NULL;
|
|
ioat->alloc_order = 0;
|
|
pci_pool_free(ioatdma_device->completion_pool,
|
|
chan->completion,
|
|
chan->completion_dma);
|
|
spin_unlock_bh(&ioat->ring_lock);
|
|
|
|
chan->last_completion = 0;
|
|
chan->completion_dma = 0;
|
|
ioat->pending = 0;
|
|
ioat->dmacount = 0;
|
|
chan->watchdog_completion = 0;
|
|
chan->last_compl_desc_addr_hw = 0;
|
|
chan->watchdog_tcp_cookie = 0;
|
|
chan->watchdog_last_tcp_cookie = 0;
|
|
}
|
|
|
|
static enum dma_status
|
|
ioat2_is_complete(struct dma_chan *c, dma_cookie_t cookie,
|
|
dma_cookie_t *done, dma_cookie_t *used)
|
|
{
|
|
struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
|
|
|
|
if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS)
|
|
return DMA_SUCCESS;
|
|
|
|
ioat2_cleanup(ioat);
|
|
|
|
return ioat_is_complete(c, cookie, done, used);
|
|
}
|
|
|
|
int __devinit ioat2_dma_probe(struct ioatdma_device *device, int dca)
|
|
{
|
|
struct pci_dev *pdev = device->pdev;
|
|
struct dma_device *dma;
|
|
struct dma_chan *c;
|
|
struct ioat_chan_common *chan;
|
|
int err;
|
|
|
|
device->enumerate_channels = ioat2_enumerate_channels;
|
|
dma = &device->common;
|
|
dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
|
|
dma->device_issue_pending = ioat2_issue_pending;
|
|
dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
|
|
dma->device_free_chan_resources = ioat2_free_chan_resources;
|
|
dma->device_is_tx_complete = ioat2_is_complete;
|
|
|
|
err = ioat_probe(device);
|
|
if (err)
|
|
return err;
|
|
ioat_set_tcp_copy_break(2048);
|
|
|
|
list_for_each_entry(c, &dma->channels, device_node) {
|
|
chan = to_chan_common(c);
|
|
writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | IOAT_DMA_DCA_ANY_CPU,
|
|
chan->reg_base + IOAT_DCACTRL_OFFSET);
|
|
}
|
|
|
|
err = ioat_register(device);
|
|
if (err)
|
|
return err;
|
|
if (dca)
|
|
device->dca = ioat2_dca_init(pdev, device->reg_base);
|
|
|
|
INIT_DELAYED_WORK(&device->work, ioat2_chan_watchdog);
|
|
schedule_delayed_work(&device->work, WATCHDOG_DELAY);
|
|
|
|
return err;
|
|
}
|
|
|
|
int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
|
|
{
|
|
struct pci_dev *pdev = device->pdev;
|
|
struct dma_device *dma;
|
|
struct dma_chan *c;
|
|
struct ioat_chan_common *chan;
|
|
int err;
|
|
u16 dev_id;
|
|
|
|
device->enumerate_channels = ioat2_enumerate_channels;
|
|
dma = &device->common;
|
|
dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock;
|
|
dma->device_issue_pending = ioat2_issue_pending;
|
|
dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
|
|
dma->device_free_chan_resources = ioat2_free_chan_resources;
|
|
dma->device_is_tx_complete = ioat2_is_complete;
|
|
|
|
/* -= IOAT ver.3 workarounds =- */
|
|
/* Write CHANERRMSK_INT with 3E07h to mask out the errors
|
|
* that can cause stability issues for IOAT ver.3
|
|
*/
|
|
pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07);
|
|
|
|
/* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
|
|
* (workaround for spurious config parity error after restart)
|
|
*/
|
|
pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id);
|
|
if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0)
|
|
pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10);
|
|
|
|
err = ioat_probe(device);
|
|
if (err)
|
|
return err;
|
|
ioat_set_tcp_copy_break(262144);
|
|
|
|
list_for_each_entry(c, &dma->channels, device_node) {
|
|
chan = to_chan_common(c);
|
|
writel(IOAT_DMA_DCA_ANY_CPU,
|
|
chan->reg_base + IOAT_DCACTRL_OFFSET);
|
|
}
|
|
|
|
err = ioat_register(device);
|
|
if (err)
|
|
return err;
|
|
if (dca)
|
|
device->dca = ioat3_dca_init(pdev, device->reg_base);
|
|
|
|
return err;
|
|
}
|