linux/include/soc/fsl/qe
Holger Brunck 067bb938da net/wan/fsl_ucc_hdlc: add hdlc-bus support
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can
be enabled with the "fsl,hdlc-bus" property in the DTS node of the
corresponding ucc.

This aligns the configuration of the UPSMR and GUMR registers to what is
done in our ucc_hdlc driver (that only support hdlc-bus mode) and with
the QuickEngine's documentation for hdlc-bus mode.

GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal
is ignored. The brkpt_support is enabled to set the HBM1 bit in the
CMXUCR register to configure an open-drain connected HDLC bus.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-05-18 10:28:39 -04:00
..
immap_qe.h soc/fsl/qe: get rid of immrbar_virt_to_phys() 2017-04-30 01:26:54 -05:00
qe.h net/wan/fsl_ucc_hdlc: add hdlc-bus support 2017-05-18 10:28:39 -04:00
qe_ic.h QE: Move QE from arch/powerpc to drivers/soc 2015-12-22 17:12:56 -06:00
qe_tdm.h fsl/qe: Do not prefix header guard with CONFIG_ 2016-06-08 11:08:01 -07:00
ucc.h fsl/qe: setup clock source for TDM mode 2016-06-07 15:56:30 -07:00
ucc_fast.h drivers/net: support hdlc function for QE-UCC 2016-06-07 15:56:31 -07:00
ucc_slow.h QE: Move QE from arch/powerpc to drivers/soc 2015-12-22 17:12:56 -06:00