5c895828f4
commit cf0b0e3712f7af90006f8317ff27278094c2c128 upstream. The POWER9 ERAT flush instruction is a SLBIA with IH=7, which is a reserved value on POWER7/8. On POWER8 this invalidates the SLB entries above index 0, similarly to SLBIA IH=0. If the SLB entries are invalidated, and then the guest is bypassed, the host SLB does not get re-loaded, so the bolted entries above 0 will be lost. This can result in kernel stack access causing a SLB fault. Kernel stack access causing a SLB fault was responsible for the infamous mega bug (search "Fix SLB reload bug"). Although since commit |
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.. | ||
Kconfig | ||
Makefile | ||
book3s.c | ||
book3s.h | ||
book3s_32_mmu.c | ||
book3s_32_mmu_host.c | ||
book3s_32_sr.S | ||
book3s_64_mmu.c | ||
book3s_64_mmu_host.c | ||
book3s_64_mmu_hv.c | ||
book3s_64_mmu_radix.c | ||
book3s_64_slb.S | ||
book3s_64_vio.c | ||
book3s_64_vio_hv.c | ||
book3s_emulate.c | ||
book3s_exports.c | ||
book3s_hv.c | ||
book3s_hv_builtin.c | ||
book3s_hv_hmi.c | ||
book3s_hv_interrupts.S | ||
book3s_hv_nested.c | ||
book3s_hv_ras.c | ||
book3s_hv_rm_mmu.c | ||
book3s_hv_rm_xics.c | ||
book3s_hv_rm_xive.c | ||
book3s_hv_rmhandlers.S | ||
book3s_hv_tm.c | ||
book3s_hv_tm_builtin.c | ||
book3s_interrupts.S | ||
book3s_mmu_hpte.c | ||
book3s_paired_singles.c | ||
book3s_pr.c | ||
book3s_pr_papr.c | ||
book3s_rmhandlers.S | ||
book3s_rtas.c | ||
book3s_segment.S | ||
book3s_xics.c | ||
book3s_xics.h | ||
book3s_xive.c | ||
book3s_xive.h | ||
book3s_xive_native.c | ||
book3s_xive_template.c | ||
booke.c | ||
booke.h | ||
booke_emulate.c | ||
booke_interrupts.S | ||
bookehv_interrupts.S | ||
e500.c | ||
e500.h | ||
e500_emulate.c | ||
e500_mmu.c | ||
e500_mmu_host.c | ||
e500_mmu_host.h | ||
e500mc.c | ||
emulate.c | ||
emulate_loadstore.c | ||
fpu.S | ||
irq.h | ||
mpic.c | ||
powerpc.c | ||
timing.c | ||
timing.h | ||
tm.S | ||
trace.h | ||
trace_book3s.h | ||
trace_booke.h | ||
trace_hv.h | ||
trace_pr.h |