Lin Huang 9dc486fdf6 clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 ... Since hclk_sd and pclk_ddr source clock from CPLL or GPLL, and these two PLL may change their frequency. If we do not assign right id to pclk_ddr and hclk_sd, they will alway use default cur register value, and may get the frequency exceed their signed off frequency. So assign correct Id for them, then we can assign frequency for them in dts. Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2018-03-23 09:09:19 +01:00
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clk-cpu.c
clk-ddr.c
clk-inverter.c
clk-mmc-phase.c	clk: rockchip: Fix error return in phase clock registration	2018-03-23 09:08:43 +01:00
clk-muxgrf.c
clk-pll.c
clk-rk3036.c
clk-rk3128.c
clk-rk3188.c
clk-rk3228.c	clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228	2018-03-23 08:49:35 +01:00
clk-rk3288.c
clk-rk3328.c	clk: rockchip: Fix wrong parents for MMC phase clock for rk3328	2018-03-23 08:58:19 +01:00
clk-rk3368.c
clk-rk3399.c	clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399	2018-03-23 09:09:19 +01:00
clk-rockchip.c
clk-rv1108.c
clk.c	clk: rockchip: Free the memory on the error path	2018-03-02 08:51:03 +01:00
clk.h
Makefile
softrst.c