2c86963b09
Back in January 2008 Nick Piggin implemented "ticket" spinlocks
for X86 (See commit 314cdbefd1).
IA64 implementation has a couple of differences because of the
available atomic operations ... e.g. we have no fetchadd2 instruction
that operates on a 16-bit quantity so we make ticket locks use
a 32-bit word for each of the current ticket and now-serving values.
Performance on uncontended locks is about 8% worse than the previous
implementation, but this seems a good trade for determinism in the
contended case. Performance impact on macro-level benchmarks is in
the noise.
Signed-off-by: Tony Luck <tony.luck@intel.com>
273 lines
6.7 KiB
C++
273 lines
6.7 KiB
C++
#ifndef _ASM_IA64_SPINLOCK_H
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#define _ASM_IA64_SPINLOCK_H
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/*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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*
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* This file is used for SMP configurations only.
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*/
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <asm/atomic.h>
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#include <asm/intrinsics.h>
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#include <asm/system.h>
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#define __raw_spin_lock_init(x) ((x)->lock = 0)
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/*
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*
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* 63 32 31 0
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* +----------------------------------------------------+
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* | next_ticket_number | now_serving |
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* +----------------------------------------------------+
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*/
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#define TICKET_SHIFT 32
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static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
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{
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int *p = (int *)&lock->lock, turn, now_serving;
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now_serving = *p;
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turn = ia64_fetchadd(1, p+1, acq);
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if (turn == now_serving)
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return;
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do {
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cpu_relax();
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} while (ACCESS_ONCE(*p) != turn);
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}
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static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock), try;
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if (!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1))) {
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try = tmp + (1L << TICKET_SHIFT);
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return ia64_cmpxchg(acq, &lock->lock, tmp, try, sizeof (tmp)) == tmp;
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}
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return 0;
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}
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static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
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{
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int *p = (int *)&lock->lock;
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(void)ia64_fetchadd(1, p, rel);
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}
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static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock);
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return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1));
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}
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static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock);
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return (((tmp >> TICKET_SHIFT) - tmp) & ((1L << TICKET_SHIFT) - 1)) > 1;
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}
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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return __ticket_spin_is_locked(lock);
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}
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static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
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{
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return __ticket_spin_is_contended(lock);
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}
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#define __raw_spin_is_contended __raw_spin_is_contended
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static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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__ticket_spin_lock(lock);
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}
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static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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return __ticket_spin_trylock(lock);
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}
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static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__ticket_spin_unlock(lock);
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}
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static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
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unsigned long flags)
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{
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__raw_spin_lock(lock);
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}
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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while (__raw_spin_is_locked(lock))
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cpu_relax();
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}
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#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
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#define __raw_write_can_lock(rw) (*(volatile int *)(rw) == 0)
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#ifdef ASM_SUPPORTED
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static __always_inline void
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__raw_read_lock_flags(raw_rwlock_t *lock, unsigned long flags)
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{
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__asm__ __volatile__ (
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"tbit.nz p6, p0 = %1,%2\n"
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"br.few 3f\n"
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"1:\n"
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"fetchadd4.rel r2 = [%0], -1;;\n"
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"(p6) ssm psr.i\n"
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"2:\n"
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"hint @pause\n"
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"ld4 r2 = [%0];;\n"
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"cmp4.lt p7,p0 = r2, r0\n"
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"(p7) br.cond.spnt.few 2b\n"
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"(p6) rsm psr.i\n"
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";;\n"
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"3:\n"
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"fetchadd4.acq r2 = [%0], 1;;\n"
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"cmp4.lt p7,p0 = r2, r0\n"
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"(p7) br.cond.spnt.few 1b\n"
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: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
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: "p6", "p7", "r2", "memory");
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}
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#define __raw_read_lock(lock) __raw_read_lock_flags(lock, 0)
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#else /* !ASM_SUPPORTED */
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#define __raw_read_lock_flags(rw, flags) __raw_read_lock(rw)
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#define __raw_read_lock(rw) \
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do { \
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raw_rwlock_t *__read_lock_ptr = (rw); \
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\
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while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
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ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
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while (*(volatile int *)__read_lock_ptr < 0) \
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cpu_relax(); \
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} \
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} while (0)
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#endif /* !ASM_SUPPORTED */
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#define __raw_read_unlock(rw) \
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do { \
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raw_rwlock_t *__read_lock_ptr = (rw); \
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ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
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} while (0)
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#ifdef ASM_SUPPORTED
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static __always_inline void
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__raw_write_lock_flags(raw_rwlock_t *lock, unsigned long flags)
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{
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__asm__ __volatile__ (
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"tbit.nz p6, p0 = %1, %2\n"
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"mov ar.ccv = r0\n"
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"dep r29 = -1, r0, 31, 1\n"
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"br.few 3f;;\n"
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"1:\n"
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"(p6) ssm psr.i\n"
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"2:\n"
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"hint @pause\n"
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"ld4 r2 = [%0];;\n"
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"cmp4.eq p0,p7 = r0, r2\n"
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"(p7) br.cond.spnt.few 2b\n"
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"(p6) rsm psr.i\n"
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";;\n"
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"3:\n"
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"cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"
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"cmp4.eq p0,p7 = r0, r2\n"
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"(p7) br.cond.spnt.few 1b;;\n"
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: : "r"(lock), "r"(flags), "i"(IA64_PSR_I_BIT)
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: "ar.ccv", "p6", "p7", "r2", "r29", "memory");
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}
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#define __raw_write_lock(rw) __raw_write_lock_flags(rw, 0)
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#define __raw_write_trylock(rw) \
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({ \
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register long result; \
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\
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__asm__ __volatile__ ( \
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"mov ar.ccv = r0\n" \
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"dep r29 = -1, r0, 31, 1;;\n" \
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"cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
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: "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
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(result == 0); \
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})
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static inline void __raw_write_unlock(raw_rwlock_t *x)
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{
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u8 *y = (u8 *)x;
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barrier();
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asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
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}
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#else /* !ASM_SUPPORTED */
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#define __raw_write_lock_flags(l, flags) __raw_write_lock(l)
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#define __raw_write_lock(l) \
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({ \
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__u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
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__u32 *ia64_write_lock_ptr = (__u32 *) (l); \
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do { \
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while (*ia64_write_lock_ptr) \
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ia64_barrier(); \
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ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
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} while (ia64_val); \
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})
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#define __raw_write_trylock(rw) \
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({ \
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__u64 ia64_val; \
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__u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
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ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
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(ia64_val == 0); \
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})
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static inline void __raw_write_unlock(raw_rwlock_t *x)
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{
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barrier();
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x->write_lock = 0;
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}
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#endif /* !ASM_SUPPORTED */
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static inline int __raw_read_trylock(raw_rwlock_t *x)
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{
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union {
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raw_rwlock_t lock;
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__u32 word;
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} old, new;
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old.lock = new.lock = *x;
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old.lock.write_lock = new.lock.write_lock = 0;
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++new.lock.read_counter;
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return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
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}
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#define _raw_spin_relax(lock) cpu_relax()
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#define _raw_read_relax(lock) cpu_relax()
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#define _raw_write_relax(lock) cpu_relax()
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#endif /* _ASM_IA64_SPINLOCK_H */
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