5c18df85d7
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
930 lines
19 KiB
C
930 lines
19 KiB
C
/*
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* linux/drivers/video/omap2/dss/core.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "CORE"
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/seq_file.h>
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#include <linux/debugfs.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <plat/display.h>
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#include <plat/clock.h>
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#include "dss.h"
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static struct {
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struct platform_device *pdev;
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int ctx_id;
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struct clk *dss_ick;
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struct clk *dss1_fck;
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struct clk *dss2_fck;
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struct clk *dss_54m_fck;
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struct clk *dss_96m_fck;
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unsigned num_clks_enabled;
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} core;
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static void dss_clk_enable_all_no_ctx(void);
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static void dss_clk_disable_all_no_ctx(void);
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static void dss_clk_enable_no_ctx(enum dss_clock clks);
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static void dss_clk_disable_no_ctx(enum dss_clock clks);
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static char *def_disp_name;
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module_param_named(def_disp, def_disp_name, charp, 0);
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MODULE_PARM_DESC(def_disp_name, "default display name");
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#ifdef DEBUG
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unsigned int dss_debug;
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module_param_named(debug, dss_debug, bool, 0644);
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#endif
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/* CONTEXT */
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static int dss_get_ctx_id(void)
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{
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struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
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int r;
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if (!pdata->get_last_off_on_transaction_id)
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return 0;
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r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
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if (r < 0) {
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dev_err(&core.pdev->dev, "getting transaction ID failed, "
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"will force context restore\n");
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r = -1;
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}
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return r;
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}
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int dss_need_ctx_restore(void)
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{
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int id = dss_get_ctx_id();
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if (id < 0 || id != core.ctx_id) {
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DSSDBG("ctx id %d -> id %d\n",
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core.ctx_id, id);
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core.ctx_id = id;
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return 1;
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} else {
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return 0;
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}
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}
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static void save_all_ctx(void)
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{
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DSSDBG("save context\n");
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dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
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dss_save_context();
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dispc_save_context();
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_save_context();
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#endif
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dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
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}
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static void restore_all_ctx(void)
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{
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DSSDBG("restore context\n");
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dss_clk_enable_all_no_ctx();
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dss_restore_context();
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dispc_restore_context();
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_restore_context();
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#endif
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dss_clk_disable_all_no_ctx();
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}
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#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
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/* CLOCKS */
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static void core_dump_clocks(struct seq_file *s)
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{
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int i;
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struct clk *clocks[5] = {
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core.dss_ick,
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core.dss1_fck,
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core.dss2_fck,
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core.dss_54m_fck,
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core.dss_96m_fck
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};
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seq_printf(s, "- CORE -\n");
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seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
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for (i = 0; i < 5; i++) {
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if (!clocks[i])
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continue;
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seq_printf(s, "%-15s\t%lu\t%d\n",
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clocks[i]->name,
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clk_get_rate(clocks[i]),
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clocks[i]->usecount);
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}
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}
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#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
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static int dss_get_clock(struct clk **clock, const char *clk_name)
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{
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struct clk *clk;
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clk = clk_get(&core.pdev->dev, clk_name);
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if (IS_ERR(clk)) {
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DSSERR("can't get clock %s", clk_name);
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return PTR_ERR(clk);
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}
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*clock = clk;
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DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
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return 0;
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}
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static int dss_get_clocks(void)
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{
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int r;
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core.dss_ick = NULL;
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core.dss1_fck = NULL;
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core.dss2_fck = NULL;
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core.dss_54m_fck = NULL;
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core.dss_96m_fck = NULL;
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r = dss_get_clock(&core.dss_ick, "ick");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss1_fck, "dss1_fck");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss2_fck, "dss2_fck");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
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if (r)
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goto err;
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r = dss_get_clock(&core.dss_96m_fck, "video_fck");
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if (r)
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goto err;
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return 0;
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err:
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if (core.dss_ick)
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clk_put(core.dss_ick);
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if (core.dss1_fck)
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clk_put(core.dss1_fck);
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if (core.dss2_fck)
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clk_put(core.dss2_fck);
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if (core.dss_54m_fck)
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clk_put(core.dss_54m_fck);
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if (core.dss_96m_fck)
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clk_put(core.dss_96m_fck);
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return r;
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}
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static void dss_put_clocks(void)
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{
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if (core.dss_96m_fck)
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clk_put(core.dss_96m_fck);
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clk_put(core.dss_54m_fck);
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clk_put(core.dss1_fck);
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clk_put(core.dss2_fck);
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clk_put(core.dss_ick);
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}
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unsigned long dss_clk_get_rate(enum dss_clock clk)
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{
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switch (clk) {
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case DSS_CLK_ICK:
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return clk_get_rate(core.dss_ick);
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case DSS_CLK_FCK1:
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return clk_get_rate(core.dss1_fck);
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case DSS_CLK_FCK2:
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return clk_get_rate(core.dss2_fck);
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case DSS_CLK_54M:
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return clk_get_rate(core.dss_54m_fck);
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case DSS_CLK_96M:
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return clk_get_rate(core.dss_96m_fck);
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}
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BUG();
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return 0;
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}
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static unsigned count_clk_bits(enum dss_clock clks)
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{
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unsigned num_clks = 0;
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if (clks & DSS_CLK_ICK)
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++num_clks;
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if (clks & DSS_CLK_FCK1)
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++num_clks;
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if (clks & DSS_CLK_FCK2)
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++num_clks;
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if (clks & DSS_CLK_54M)
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++num_clks;
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if (clks & DSS_CLK_96M)
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++num_clks;
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return num_clks;
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}
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static void dss_clk_enable_no_ctx(enum dss_clock clks)
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{
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unsigned num_clks = count_clk_bits(clks);
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if (clks & DSS_CLK_ICK)
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clk_enable(core.dss_ick);
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if (clks & DSS_CLK_FCK1)
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clk_enable(core.dss1_fck);
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if (clks & DSS_CLK_FCK2)
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clk_enable(core.dss2_fck);
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if (clks & DSS_CLK_54M)
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clk_enable(core.dss_54m_fck);
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if (clks & DSS_CLK_96M)
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clk_enable(core.dss_96m_fck);
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core.num_clks_enabled += num_clks;
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}
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void dss_clk_enable(enum dss_clock clks)
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{
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dss_clk_enable_no_ctx(clks);
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if (cpu_is_omap34xx() && dss_need_ctx_restore())
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restore_all_ctx();
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}
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static void dss_clk_disable_no_ctx(enum dss_clock clks)
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{
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unsigned num_clks = count_clk_bits(clks);
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if (clks & DSS_CLK_ICK)
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clk_disable(core.dss_ick);
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if (clks & DSS_CLK_FCK1)
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clk_disable(core.dss1_fck);
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if (clks & DSS_CLK_FCK2)
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clk_disable(core.dss2_fck);
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if (clks & DSS_CLK_54M)
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clk_disable(core.dss_54m_fck);
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if (clks & DSS_CLK_96M)
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clk_disable(core.dss_96m_fck);
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core.num_clks_enabled -= num_clks;
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}
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void dss_clk_disable(enum dss_clock clks)
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{
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if (cpu_is_omap34xx()) {
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unsigned num_clks = count_clk_bits(clks);
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BUG_ON(core.num_clks_enabled < num_clks);
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if (core.num_clks_enabled == num_clks)
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save_all_ctx();
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}
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dss_clk_disable_no_ctx(clks);
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}
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static void dss_clk_enable_all_no_ctx(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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dss_clk_enable_no_ctx(clks);
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}
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static void dss_clk_disable_all_no_ctx(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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dss_clk_disable_no_ctx(clks);
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}
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static void dss_clk_disable_all(void)
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{
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enum dss_clock clks;
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clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
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if (cpu_is_omap34xx())
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clks |= DSS_CLK_96M;
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dss_clk_disable(clks);
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}
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/* DEBUGFS */
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#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
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static void dss_debug_dump_clocks(struct seq_file *s)
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{
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core_dump_clocks(s);
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dss_dump_clocks(s);
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dispc_dump_clocks(s);
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#ifdef CONFIG_OMAP2_DSS_DSI
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dsi_dump_clocks(s);
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#endif
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}
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static int dss_debug_show(struct seq_file *s, void *unused)
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{
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void (*func)(struct seq_file *) = s->private;
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func(s);
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return 0;
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}
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static int dss_debug_open(struct inode *inode, struct file *file)
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{
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return single_open(file, dss_debug_show, inode->i_private);
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}
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static const struct file_operations dss_debug_fops = {
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.open = dss_debug_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static struct dentry *dss_debugfs_dir;
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static int dss_initialize_debugfs(void)
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{
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dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
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if (IS_ERR(dss_debugfs_dir)) {
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int err = PTR_ERR(dss_debugfs_dir);
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dss_debugfs_dir = NULL;
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return err;
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}
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debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
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&dss_debug_dump_clocks, &dss_debug_fops);
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debugfs_create_file("dispc_irq", S_IRUGO, dss_debugfs_dir,
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&dispc_dump_irqs, &dss_debug_fops);
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#ifdef CONFIG_OMAP2_DSS_DSI
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debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
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&dsi_dump_irqs, &dss_debug_fops);
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#endif
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debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
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&dss_dump_regs, &dss_debug_fops);
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debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
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&dispc_dump_regs, &dss_debug_fops);
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#ifdef CONFIG_OMAP2_DSS_RFBI
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debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
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&rfbi_dump_regs, &dss_debug_fops);
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#endif
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#ifdef CONFIG_OMAP2_DSS_DSI
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debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
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&dsi_dump_regs, &dss_debug_fops);
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#endif
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#ifdef CONFIG_OMAP2_DSS_VENC
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debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
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&venc_dump_regs, &dss_debug_fops);
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#endif
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return 0;
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}
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static void dss_uninitialize_debugfs(void)
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{
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if (dss_debugfs_dir)
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debugfs_remove_recursive(dss_debugfs_dir);
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}
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#endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
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/* PLATFORM DEVICE */
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static int omap_dss_probe(struct platform_device *pdev)
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{
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struct omap_dss_board_info *pdata = pdev->dev.platform_data;
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int skip_init = 0;
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int r;
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int i;
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core.pdev = pdev;
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dss_init_overlay_managers(pdev);
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dss_init_overlays(pdev);
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r = dss_get_clocks();
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if (r)
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goto fail0;
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dss_clk_enable_all_no_ctx();
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core.ctx_id = dss_get_ctx_id();
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DSSDBG("initial ctx id %u\n", core.ctx_id);
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#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
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/* DISPC_CONTROL */
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if (omap_readl(0x48050440) & 1) /* LCD enabled? */
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skip_init = 1;
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#endif
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r = dss_init(skip_init);
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if (r) {
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DSSERR("Failed to initialize DSS\n");
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goto fail0;
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}
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#ifdef CONFIG_OMAP2_DSS_RFBI
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r = rfbi_init();
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if (r) {
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DSSERR("Failed to initialize rfbi\n");
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goto fail0;
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}
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#endif
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r = dpi_init();
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if (r) {
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DSSERR("Failed to initialize dpi\n");
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goto fail0;
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}
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r = dispc_init();
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if (r) {
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DSSERR("Failed to initialize dispc\n");
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goto fail0;
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}
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#ifdef CONFIG_OMAP2_DSS_VENC
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r = venc_init(pdev);
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if (r) {
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DSSERR("Failed to initialize venc\n");
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goto fail0;
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}
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#endif
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if (cpu_is_omap34xx()) {
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#ifdef CONFIG_OMAP2_DSS_SDI
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r = sdi_init(skip_init);
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if (r) {
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DSSERR("Failed to initialize SDI\n");
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goto fail0;
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}
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#endif
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#ifdef CONFIG_OMAP2_DSS_DSI
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r = dsi_init(pdev);
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if (r) {
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DSSERR("Failed to initialize DSI\n");
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goto fail0;
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}
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#endif
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}
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#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
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r = dss_initialize_debugfs();
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if (r)
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goto fail0;
|
|
#endif
|
|
|
|
for (i = 0; i < pdata->num_devices; ++i) {
|
|
struct omap_dss_device *dssdev = pdata->devices[i];
|
|
|
|
r = omap_dss_register_device(dssdev);
|
|
if (r)
|
|
DSSERR("device reg failed %d\n", i);
|
|
|
|
if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
|
|
pdata->default_device = dssdev;
|
|
}
|
|
|
|
dss_clk_disable_all();
|
|
|
|
return 0;
|
|
|
|
/* XXX fail correctly */
|
|
fail0:
|
|
return r;
|
|
}
|
|
|
|
static int omap_dss_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_dss_board_info *pdata = pdev->dev.platform_data;
|
|
int i;
|
|
int c;
|
|
|
|
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
|
dss_uninitialize_debugfs();
|
|
#endif
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_VENC
|
|
venc_exit();
|
|
#endif
|
|
dispc_exit();
|
|
dpi_exit();
|
|
#ifdef CONFIG_OMAP2_DSS_RFBI
|
|
rfbi_exit();
|
|
#endif
|
|
if (cpu_is_omap34xx()) {
|
|
#ifdef CONFIG_OMAP2_DSS_DSI
|
|
dsi_exit();
|
|
#endif
|
|
#ifdef CONFIG_OMAP2_DSS_SDI
|
|
sdi_exit();
|
|
#endif
|
|
}
|
|
|
|
dss_exit();
|
|
|
|
/* these should be removed at some point */
|
|
c = core.dss_ick->usecount;
|
|
if (c > 0) {
|
|
DSSERR("warning: dss_ick usecount %d, disabling\n", c);
|
|
while (c-- > 0)
|
|
clk_disable(core.dss_ick);
|
|
}
|
|
|
|
c = core.dss1_fck->usecount;
|
|
if (c > 0) {
|
|
DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
|
|
while (c-- > 0)
|
|
clk_disable(core.dss1_fck);
|
|
}
|
|
|
|
c = core.dss2_fck->usecount;
|
|
if (c > 0) {
|
|
DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
|
|
while (c-- > 0)
|
|
clk_disable(core.dss2_fck);
|
|
}
|
|
|
|
c = core.dss_54m_fck->usecount;
|
|
if (c > 0) {
|
|
DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
|
|
while (c-- > 0)
|
|
clk_disable(core.dss_54m_fck);
|
|
}
|
|
|
|
if (core.dss_96m_fck) {
|
|
c = core.dss_96m_fck->usecount;
|
|
if (c > 0) {
|
|
DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
|
|
c);
|
|
while (c-- > 0)
|
|
clk_disable(core.dss_96m_fck);
|
|
}
|
|
}
|
|
|
|
dss_put_clocks();
|
|
|
|
dss_uninit_overlays(pdev);
|
|
dss_uninit_overlay_managers(pdev);
|
|
|
|
for (i = 0; i < pdata->num_devices; ++i)
|
|
omap_dss_unregister_device(pdata->devices[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_dss_shutdown(struct platform_device *pdev)
|
|
{
|
|
DSSDBG("shutdown\n");
|
|
dss_disable_all_devices();
|
|
}
|
|
|
|
static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
DSSDBG("suspend %d\n", state.event);
|
|
|
|
return dss_suspend_all_devices();
|
|
}
|
|
|
|
static int omap_dss_resume(struct platform_device *pdev)
|
|
{
|
|
DSSDBG("resume\n");
|
|
|
|
return dss_resume_all_devices();
|
|
}
|
|
|
|
static struct platform_driver omap_dss_driver = {
|
|
.probe = omap_dss_probe,
|
|
.remove = omap_dss_remove,
|
|
.shutdown = omap_dss_shutdown,
|
|
.suspend = omap_dss_suspend,
|
|
.resume = omap_dss_resume,
|
|
.driver = {
|
|
.name = "omapdss",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
/* BUS */
|
|
static int dss_bus_match(struct device *dev, struct device_driver *driver)
|
|
{
|
|
struct omap_dss_device *dssdev = to_dss_device(dev);
|
|
|
|
DSSDBG("bus_match. dev %s/%s, drv %s\n",
|
|
dev_name(dev), dssdev->driver_name, driver->name);
|
|
|
|
return strcmp(dssdev->driver_name, driver->name) == 0;
|
|
}
|
|
|
|
static ssize_t device_name_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct omap_dss_device *dssdev = to_dss_device(dev);
|
|
return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
dssdev->name ?
|
|
dssdev->name : "");
|
|
}
|
|
|
|
static struct device_attribute default_dev_attrs[] = {
|
|
__ATTR(name, S_IRUGO, device_name_show, NULL),
|
|
__ATTR_NULL,
|
|
};
|
|
|
|
static ssize_t driver_name_show(struct device_driver *drv, char *buf)
|
|
{
|
|
struct omap_dss_driver *dssdrv = to_dss_driver(drv);
|
|
return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
dssdrv->driver.name ?
|
|
dssdrv->driver.name : "");
|
|
}
|
|
static struct driver_attribute default_drv_attrs[] = {
|
|
__ATTR(name, S_IRUGO, driver_name_show, NULL),
|
|
__ATTR_NULL,
|
|
};
|
|
|
|
static struct bus_type dss_bus_type = {
|
|
.name = "omapdss",
|
|
.match = dss_bus_match,
|
|
.dev_attrs = default_dev_attrs,
|
|
.drv_attrs = default_drv_attrs,
|
|
};
|
|
|
|
static void dss_bus_release(struct device *dev)
|
|
{
|
|
DSSDBG("bus_release\n");
|
|
}
|
|
|
|
static struct device dss_bus = {
|
|
.release = dss_bus_release,
|
|
};
|
|
|
|
struct bus_type *dss_get_bus(void)
|
|
{
|
|
return &dss_bus_type;
|
|
}
|
|
|
|
/* DRIVER */
|
|
static int dss_driver_probe(struct device *dev)
|
|
{
|
|
int r;
|
|
struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
|
|
struct omap_dss_device *dssdev = to_dss_device(dev);
|
|
struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
|
|
bool force;
|
|
|
|
DSSDBG("driver_probe: dev %s/%s, drv %s\n",
|
|
dev_name(dev), dssdev->driver_name,
|
|
dssdrv->driver.name);
|
|
|
|
dss_init_device(core.pdev, dssdev);
|
|
|
|
/* skip this if the device is behind a ctrl */
|
|
if (!dssdev->panel.ctrl) {
|
|
force = pdata->default_device == dssdev;
|
|
dss_recheck_connections(dssdev, force);
|
|
}
|
|
|
|
r = dssdrv->probe(dssdev);
|
|
|
|
if (r) {
|
|
DSSERR("driver probe failed: %d\n", r);
|
|
return r;
|
|
}
|
|
|
|
DSSDBG("probe done for device %s\n", dev_name(dev));
|
|
|
|
dssdev->driver = dssdrv;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dss_driver_remove(struct device *dev)
|
|
{
|
|
struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
|
|
struct omap_dss_device *dssdev = to_dss_device(dev);
|
|
|
|
DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
|
|
dssdev->driver_name);
|
|
|
|
dssdrv->remove(dssdev);
|
|
|
|
dss_uninit_device(core.pdev, dssdev);
|
|
|
|
dssdev->driver = NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
|
|
{
|
|
dssdriver->driver.bus = &dss_bus_type;
|
|
dssdriver->driver.probe = dss_driver_probe;
|
|
dssdriver->driver.remove = dss_driver_remove;
|
|
return driver_register(&dssdriver->driver);
|
|
}
|
|
EXPORT_SYMBOL(omap_dss_register_driver);
|
|
|
|
void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
|
|
{
|
|
driver_unregister(&dssdriver->driver);
|
|
}
|
|
EXPORT_SYMBOL(omap_dss_unregister_driver);
|
|
|
|
/* DEVICE */
|
|
static void reset_device(struct device *dev, int check)
|
|
{
|
|
u8 *dev_p = (u8 *)dev;
|
|
u8 *dev_end = dev_p + sizeof(*dev);
|
|
void *saved_pdata;
|
|
|
|
saved_pdata = dev->platform_data;
|
|
if (check) {
|
|
/*
|
|
* Check if there is any other setting than platform_data
|
|
* in struct device; warn that these will be reset by our
|
|
* init.
|
|
*/
|
|
dev->platform_data = NULL;
|
|
while (dev_p < dev_end) {
|
|
if (*dev_p) {
|
|
WARN("%s: struct device fields will be "
|
|
"discarded\n",
|
|
__func__);
|
|
break;
|
|
}
|
|
dev_p++;
|
|
}
|
|
}
|
|
memset(dev, 0, sizeof(*dev));
|
|
dev->platform_data = saved_pdata;
|
|
}
|
|
|
|
|
|
static void omap_dss_dev_release(struct device *dev)
|
|
{
|
|
reset_device(dev, 0);
|
|
}
|
|
|
|
int omap_dss_register_device(struct omap_dss_device *dssdev)
|
|
{
|
|
static int dev_num;
|
|
static int panel_num;
|
|
int r;
|
|
|
|
WARN_ON(!dssdev->driver_name);
|
|
|
|
reset_device(&dssdev->dev, 1);
|
|
dssdev->dev.bus = &dss_bus_type;
|
|
dssdev->dev.parent = &dss_bus;
|
|
dssdev->dev.release = omap_dss_dev_release;
|
|
dev_set_name(&dssdev->dev, "display%d", dev_num++);
|
|
r = device_register(&dssdev->dev);
|
|
if (r)
|
|
return r;
|
|
|
|
if (dssdev->ctrl.panel) {
|
|
struct omap_dss_device *panel = dssdev->ctrl.panel;
|
|
|
|
panel->panel.ctrl = dssdev;
|
|
|
|
reset_device(&panel->dev, 1);
|
|
panel->dev.bus = &dss_bus_type;
|
|
panel->dev.parent = &dssdev->dev;
|
|
panel->dev.release = omap_dss_dev_release;
|
|
dev_set_name(&panel->dev, "panel%d", panel_num++);
|
|
r = device_register(&panel->dev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void omap_dss_unregister_device(struct omap_dss_device *dssdev)
|
|
{
|
|
device_unregister(&dssdev->dev);
|
|
|
|
if (dssdev->ctrl.panel) {
|
|
struct omap_dss_device *panel = dssdev->ctrl.panel;
|
|
device_unregister(&panel->dev);
|
|
}
|
|
}
|
|
|
|
/* BUS */
|
|
static int omap_dss_bus_register(void)
|
|
{
|
|
int r;
|
|
|
|
r = bus_register(&dss_bus_type);
|
|
if (r) {
|
|
DSSERR("bus register failed\n");
|
|
return r;
|
|
}
|
|
|
|
dev_set_name(&dss_bus, "omapdss");
|
|
r = device_register(&dss_bus);
|
|
if (r) {
|
|
DSSERR("bus driver register failed\n");
|
|
bus_unregister(&dss_bus_type);
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* INIT */
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_MODULE
|
|
static void omap_dss_bus_unregister(void)
|
|
{
|
|
device_unregister(&dss_bus);
|
|
|
|
bus_unregister(&dss_bus_type);
|
|
}
|
|
|
|
static int __init omap_dss_init(void)
|
|
{
|
|
int r;
|
|
|
|
r = omap_dss_bus_register();
|
|
if (r)
|
|
return r;
|
|
|
|
r = platform_driver_register(&omap_dss_driver);
|
|
if (r) {
|
|
omap_dss_bus_unregister();
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit omap_dss_exit(void)
|
|
{
|
|
platform_driver_unregister(&omap_dss_driver);
|
|
|
|
omap_dss_bus_unregister();
|
|
}
|
|
|
|
module_init(omap_dss_init);
|
|
module_exit(omap_dss_exit);
|
|
#else
|
|
static int __init omap_dss_init(void)
|
|
{
|
|
return omap_dss_bus_register();
|
|
}
|
|
|
|
static int __init omap_dss_init2(void)
|
|
{
|
|
return platform_driver_register(&omap_dss_driver);
|
|
}
|
|
|
|
core_initcall(omap_dss_init);
|
|
device_initcall(omap_dss_init2);
|
|
#endif
|
|
|
|
MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
|
|
MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
|
|
MODULE_LICENSE("GPL v2");
|
|
|