693 lines
17 KiB
C
693 lines
17 KiB
C
/* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
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* pci.c: UltraSparc PCI controller support.
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*
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* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
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* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/capability.h>
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#include <linux/errno.h>
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#include <linux/smp_lock.h>
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#include <linux/msi.h>
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <asm/uaccess.h>
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#include <asm/pbm.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/ebus.h>
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#include <asm/isa.h>
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#include <asm/prom.h>
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unsigned long pci_memspace_mask = 0xffffffffUL;
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#ifndef CONFIG_PCI
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/* A "nop" PCI implementation. */
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asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
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unsigned long off, unsigned long len,
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unsigned char *buf)
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{
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return 0;
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}
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asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
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unsigned long off, unsigned long len,
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unsigned char *buf)
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{
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return 0;
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}
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#else
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/* List of all PCI controllers found in the system. */
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struct pci_controller_info *pci_controller_root = NULL;
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/* Each PCI controller found gets a unique index. */
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int pci_num_controllers = 0;
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volatile int pci_poke_in_progress;
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volatile int pci_poke_cpu = -1;
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volatile int pci_poke_faulted;
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static DEFINE_SPINLOCK(pci_poke_lock);
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void pci_config_read8(u8 *addr, u8 *ret)
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{
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unsigned long flags;
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u8 byte;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"lduba [%1] %2, %0\n\t"
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"membar #Sync"
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: "=r" (byte)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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if (!pci_poke_faulted)
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*ret = byte;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_read16(u16 *addr, u16 *ret)
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{
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unsigned long flags;
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u16 word;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"lduha [%1] %2, %0\n\t"
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"membar #Sync"
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: "=r" (word)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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if (!pci_poke_faulted)
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*ret = word;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_read32(u32 *addr, u32 *ret)
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{
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unsigned long flags;
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u32 dword;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"lduwa [%1] %2, %0\n\t"
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"membar #Sync"
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: "=r" (dword)
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: "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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if (!pci_poke_faulted)
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*ret = dword;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_write8(u8 *addr, u8 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"stba %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_write16(u16 *addr, u16 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"stha %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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void pci_config_write32(u32 *addr, u32 val)
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{
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unsigned long flags;
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spin_lock_irqsave(&pci_poke_lock, flags);
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pci_poke_cpu = smp_processor_id();
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pci_poke_in_progress = 1;
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pci_poke_faulted = 0;
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__asm__ __volatile__("membar #Sync\n\t"
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"stwa %0, [%1] %2\n\t"
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"membar #Sync"
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: /* no outputs */
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: "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
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: "memory");
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pci_poke_in_progress = 0;
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pci_poke_cpu = -1;
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spin_unlock_irqrestore(&pci_poke_lock, flags);
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}
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/* Probe for all PCI controllers in the system. */
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extern void sabre_init(struct device_node *, const char *);
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extern void psycho_init(struct device_node *, const char *);
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extern void schizo_init(struct device_node *, const char *);
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extern void schizo_plus_init(struct device_node *, const char *);
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extern void tomatillo_init(struct device_node *, const char *);
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extern void sun4v_pci_init(struct device_node *, const char *);
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static struct {
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char *model_name;
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void (*init)(struct device_node *, const char *);
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} pci_controller_table[] __initdata = {
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{ "SUNW,sabre", sabre_init },
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{ "pci108e,a000", sabre_init },
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{ "pci108e,a001", sabre_init },
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{ "SUNW,psycho", psycho_init },
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{ "pci108e,8000", psycho_init },
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{ "SUNW,schizo", schizo_init },
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{ "pci108e,8001", schizo_init },
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{ "SUNW,schizo+", schizo_plus_init },
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{ "pci108e,8002", schizo_plus_init },
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{ "SUNW,tomatillo", tomatillo_init },
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{ "pci108e,a801", tomatillo_init },
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{ "SUNW,sun4v-pci", sun4v_pci_init },
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};
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#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
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sizeof(pci_controller_table[0]))
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static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
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{
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int i;
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for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
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if (!strncmp(model_name,
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pci_controller_table[i].model_name,
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namelen)) {
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pci_controller_table[i].init(dp, model_name);
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return 1;
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}
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}
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return 0;
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}
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static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
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{
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int i;
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for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
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if (!strncmp(model_name,
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pci_controller_table[i].model_name,
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namelen)) {
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return 1;
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}
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}
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return 0;
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}
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static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
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{
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struct device_node *dp;
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int count = 0;
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for_each_node_by_name(dp, "pci") {
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struct property *prop;
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int len;
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prop = of_find_property(dp, "model", &len);
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if (!prop)
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prop = of_find_property(dp, "compatible", &len);
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if (prop) {
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const char *model = prop->value;
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int item_len = 0;
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/* Our value may be a multi-valued string in the
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* case of some compatible properties. For sanity,
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* only try the first one.
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*/
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while (model[item_len] && len) {
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len--;
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item_len++;
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}
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if (handler(model, item_len, dp))
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count++;
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}
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}
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return count;
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}
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/* Is there some PCI controller in the system? */
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int __init pcic_present(void)
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{
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return pci_controller_scan(pci_is_controller);
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}
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struct pci_iommu_ops *pci_iommu_ops;
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EXPORT_SYMBOL(pci_iommu_ops);
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extern struct pci_iommu_ops pci_sun4u_iommu_ops,
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pci_sun4v_iommu_ops;
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/* Find each controller in the system, attach and initialize
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* software state structure for each and link into the
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* pci_controller_root. Setup the controller enough such
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* that bus scanning can be done.
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*/
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static void __init pci_controller_probe(void)
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{
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if (tlb_type == hypervisor)
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pci_iommu_ops = &pci_sun4v_iommu_ops;
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else
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pci_iommu_ops = &pci_sun4u_iommu_ops;
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printk("PCI: Probing for controllers.\n");
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pci_controller_scan(pci_controller_init);
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}
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static void __init pci_scan_each_controller_bus(void)
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{
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struct pci_controller_info *p;
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for (p = pci_controller_root; p; p = p->next)
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p->scan_bus(p);
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}
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extern void power_init(void);
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static int __init pcibios_init(void)
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{
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pci_controller_probe();
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if (pci_controller_root == NULL)
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return 0;
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pci_scan_each_controller_bus();
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isa_init();
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ebus_init();
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power_init();
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return 0;
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}
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subsys_initcall(pcibios_init);
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void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
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{
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struct pci_pbm_info *pbm = pbus->sysdata;
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/* Generic PCI bus probing sets these to point at
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* &io{port,mem}_resouce which is wrong for us.
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*/
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pbus->resource[0] = &pbm->io_space;
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pbus->resource[1] = &pbm->mem_space;
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}
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struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
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{
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struct pci_pbm_info *pbm = pdev->bus->sysdata;
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struct resource *root = NULL;
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if (r->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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if (r->flags & IORESOURCE_MEM)
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root = &pbm->mem_space;
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return root;
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}
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void pcibios_update_irq(struct pci_dev *pdev, int irq)
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{
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}
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void pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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}
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int pcibios_enable_device(struct pci_dev *pdev, int mask)
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{
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return 0;
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}
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void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_pbm_info *pbm = pdev->bus->sysdata;
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struct resource zero_res, *root;
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zero_res.start = 0;
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zero_res.end = 0;
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zero_res.flags = res->flags;
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if (res->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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else
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root = &pbm->mem_space;
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pbm->parent->resource_adjust(pdev, &zero_res, root);
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region->start = res->start - zero_res.start;
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region->end = res->end - zero_res.start;
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}
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
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struct pci_bus_region *region)
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{
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struct pci_pbm_info *pbm = pdev->bus->sysdata;
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struct resource *root;
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res->start = region->start;
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res->end = region->end;
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if (res->flags & IORESOURCE_IO)
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root = &pbm->io_space;
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else
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root = &pbm->mem_space;
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pbm->parent->resource_adjust(pdev, res, root);
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}
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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char * __devinit pcibios_setup(char *str)
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{
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return str;
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}
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/* Platform support for /proc/bus/pci/X/Y mmap()s. */
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/* If the user uses a host-bridge as the PCI device, he may use
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* this to perform a raw mmap() of the I/O or MEM space behind
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* that controller.
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*
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* This can be useful for execution of x86 PCI bios initialization code
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* on a PCI card, like the xfree86 int10 stuff does.
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*/
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static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state)
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{
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struct pcidev_cookie *pcp = pdev->sysdata;
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struct pci_pbm_info *pbm;
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struct pci_controller_info *p;
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unsigned long space_size, user_offset, user_size;
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if (!pcp)
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return -ENXIO;
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pbm = pcp->pbm;
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if (!pbm)
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return -ENXIO;
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p = pbm->parent;
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if (p->pbms_same_domain) {
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unsigned long lowest, highest;
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lowest = ~0UL; highest = 0UL;
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if (mmap_state == pci_mmap_io) {
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if (p->pbm_A.io_space.flags) {
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lowest = p->pbm_A.io_space.start;
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highest = p->pbm_A.io_space.end + 1;
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}
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if (p->pbm_B.io_space.flags) {
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if (lowest > p->pbm_B.io_space.start)
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lowest = p->pbm_B.io_space.start;
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if (highest < p->pbm_B.io_space.end + 1)
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highest = p->pbm_B.io_space.end + 1;
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}
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space_size = highest - lowest;
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} else {
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if (p->pbm_A.mem_space.flags) {
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lowest = p->pbm_A.mem_space.start;
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highest = p->pbm_A.mem_space.end + 1;
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}
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if (p->pbm_B.mem_space.flags) {
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if (lowest > p->pbm_B.mem_space.start)
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lowest = p->pbm_B.mem_space.start;
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if (highest < p->pbm_B.mem_space.end + 1)
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highest = p->pbm_B.mem_space.end + 1;
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}
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space_size = highest - lowest;
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}
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} else {
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if (mmap_state == pci_mmap_io) {
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space_size = (pbm->io_space.end -
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pbm->io_space.start) + 1;
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} else {
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space_size = (pbm->mem_space.end -
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pbm->mem_space.start) + 1;
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}
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}
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/* Make sure the request is in range. */
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user_offset = vma->vm_pgoff << PAGE_SHIFT;
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user_size = vma->vm_end - vma->vm_start;
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if (user_offset >= space_size ||
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(user_offset + user_size) > space_size)
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return -EINVAL;
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if (p->pbms_same_domain) {
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unsigned long lowest = ~0UL;
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if (mmap_state == pci_mmap_io) {
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if (p->pbm_A.io_space.flags)
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lowest = p->pbm_A.io_space.start;
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if (p->pbm_B.io_space.flags &&
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lowest > p->pbm_B.io_space.start)
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lowest = p->pbm_B.io_space.start;
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} else {
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if (p->pbm_A.mem_space.flags)
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lowest = p->pbm_A.mem_space.start;
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if (p->pbm_B.mem_space.flags &&
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lowest > p->pbm_B.mem_space.start)
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lowest = p->pbm_B.mem_space.start;
|
|
}
|
|
vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
|
|
} else {
|
|
if (mmap_state == pci_mmap_io) {
|
|
vma->vm_pgoff = (pbm->io_space.start +
|
|
user_offset) >> PAGE_SHIFT;
|
|
} else {
|
|
vma->vm_pgoff = (pbm->mem_space.start +
|
|
user_offset) >> PAGE_SHIFT;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
|
|
* to the 32-bit pci bus offset for DEV requested by the user.
|
|
*
|
|
* Basically, the user finds the base address for his device which he wishes
|
|
* to mmap. They read the 32-bit value from the config space base register,
|
|
* add whatever PAGE_SIZE multiple offset they wish, and feed this into the
|
|
* offset parameter of mmap on /proc/bus/pci/XXX for that device.
|
|
*
|
|
* Returns negative error code on failure, zero on success.
|
|
*/
|
|
static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state)
|
|
{
|
|
unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
|
|
unsigned long user32 = user_offset & pci_memspace_mask;
|
|
unsigned long largest_base, this_base, addr32;
|
|
int i;
|
|
|
|
if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
|
|
return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
|
|
|
|
/* Figure out which base address this is for. */
|
|
largest_base = 0UL;
|
|
for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
|
|
struct resource *rp = &dev->resource[i];
|
|
|
|
/* Active? */
|
|
if (!rp->flags)
|
|
continue;
|
|
|
|
/* Same type? */
|
|
if (i == PCI_ROM_RESOURCE) {
|
|
if (mmap_state != pci_mmap_mem)
|
|
continue;
|
|
} else {
|
|
if ((mmap_state == pci_mmap_io &&
|
|
(rp->flags & IORESOURCE_IO) == 0) ||
|
|
(mmap_state == pci_mmap_mem &&
|
|
(rp->flags & IORESOURCE_MEM) == 0))
|
|
continue;
|
|
}
|
|
|
|
this_base = rp->start;
|
|
|
|
addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
|
|
|
|
if (mmap_state == pci_mmap_io)
|
|
addr32 &= 0xffffff;
|
|
|
|
if (addr32 <= user32 && this_base > largest_base)
|
|
largest_base = this_base;
|
|
}
|
|
|
|
if (largest_base == 0UL)
|
|
return -EINVAL;
|
|
|
|
/* Now construct the final physical address. */
|
|
if (mmap_state == pci_mmap_io)
|
|
vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
|
|
else
|
|
vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
|
|
* mapping.
|
|
*/
|
|
static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state)
|
|
{
|
|
vma->vm_flags |= (VM_IO | VM_RESERVED);
|
|
}
|
|
|
|
/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
|
|
* device mapping.
|
|
*/
|
|
static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state)
|
|
{
|
|
/* Our io_remap_pfn_range takes care of this, do nothing. */
|
|
}
|
|
|
|
/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
|
|
* for this architecture. The region in the process to map is described by vm_start
|
|
* and vm_end members of VMA, the base physical address is found in vm_pgoff.
|
|
* The pci device structure is provided so that architectures may make mapping
|
|
* decisions on a per-device or per-bus basis.
|
|
*
|
|
* Returns a negative error code on failure, zero on success.
|
|
*/
|
|
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
|
enum pci_mmap_state mmap_state,
|
|
int write_combine)
|
|
{
|
|
int ret;
|
|
|
|
ret = __pci_mmap_make_offset(dev, vma, mmap_state);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
__pci_mmap_set_flags(dev, vma, mmap_state);
|
|
__pci_mmap_set_pgprot(dev, vma, mmap_state);
|
|
|
|
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
|
ret = io_remap_pfn_range(vma, vma->vm_start,
|
|
vma->vm_pgoff,
|
|
vma->vm_end - vma->vm_start,
|
|
vma->vm_page_prot);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Return the domain nuber for this pci bus */
|
|
|
|
int pci_domain_nr(struct pci_bus *pbus)
|
|
{
|
|
struct pci_pbm_info *pbm = pbus->sysdata;
|
|
int ret;
|
|
|
|
if (pbm == NULL || pbm->parent == NULL) {
|
|
ret = -ENXIO;
|
|
} else {
|
|
struct pci_controller_info *p = pbm->parent;
|
|
|
|
ret = p->index;
|
|
if (p->pbms_same_domain == 0)
|
|
ret = ((ret << 1) +
|
|
((pbm == &pbm->parent->pbm_B) ? 1 : 0));
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(pci_domain_nr);
|
|
|
|
#ifdef CONFIG_PCI_MSI
|
|
int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
|
|
{
|
|
struct pcidev_cookie *pcp = pdev->sysdata;
|
|
struct pci_pbm_info *pbm = pcp->pbm;
|
|
struct pci_controller_info *p = pbm->parent;
|
|
int virt_irq, err;
|
|
|
|
if (!pbm->msi_num || !p->setup_msi_irq)
|
|
return -EINVAL;
|
|
|
|
err = p->setup_msi_irq(&virt_irq, pdev, desc);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return virt_irq;
|
|
}
|
|
|
|
void arch_teardown_msi_irq(unsigned int virt_irq)
|
|
{
|
|
struct msi_desc *entry = get_irq_msi(virt_irq);
|
|
struct pci_dev *pdev = entry->dev;
|
|
struct pcidev_cookie *pcp = pdev->sysdata;
|
|
struct pci_pbm_info *pbm = pcp->pbm;
|
|
struct pci_controller_info *p = pbm->parent;
|
|
|
|
if (!pbm->msi_num || !p->setup_msi_irq)
|
|
return;
|
|
|
|
return p->teardown_msi_irq(virt_irq, pdev);
|
|
}
|
|
#endif /* !(CONFIG_PCI_MSI) */
|
|
|
|
struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
|
|
{
|
|
struct pcidev_cookie *pc = pdev->sysdata;
|
|
|
|
return pc->op->node;
|
|
}
|
|
EXPORT_SYMBOL(pci_device_to_OF_node);
|
|
|
|
#endif /* !(CONFIG_PCI) */
|