342 lines
8.3 KiB
C
342 lines
8.3 KiB
C
/*
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* Board setup routines for the Motorola MVME5100.
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/seq_file.h>
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#include <linux/kdev_t.h>
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#include <linux/root_dev.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/open_pic.h>
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#include <asm/i8259.h>
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#include <asm/todc.h>
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#include <asm/pci-bridge.h>
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#include <asm/bootinfo.h>
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#include <asm/hawk.h>
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#include <platforms/pplus.h>
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#include <platforms/mvme5100.h>
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static u_char mvme5100_openpic_initsenses[16] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* i8259 cascade */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* TL16C550 UART 1,2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet1 front panel or P2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Hawk Watchdog 1,2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* DS1621 thermal alarm */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT0# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT1# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT2# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT3# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTA#, PMC2 INTB# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTB#, PMC2 INTC# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTC#, PMC2 INTD# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTD#, PMC2 INTA# */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet 2 (front panel) */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Abort Switch */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* RTC Alarm */
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};
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static inline int
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mvme5100_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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int irq;
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 0, 0, 0, 0 }, /* IDSEL 11 - Winbond */
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{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
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{ 21, 22, 23, 24 }, /* IDSEL 13 - Universe II */
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{ 18, 0, 0, 0 }, /* IDSEL 14 - Enet 1 */
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{ 0, 0, 0, 0 }, /* IDSEL 15 - unused */
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{ 25, 26, 27, 28 }, /* IDSEL 16 - PMC Slot 1 */
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{ 28, 25, 26, 27 }, /* IDSEL 17 - PMC Slot 2 */
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{ 0, 0, 0, 0 }, /* IDSEL 18 - unused */
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{ 29, 0, 0, 0 }, /* IDSEL 19 - Enet 2 */
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{ 0, 0, 0, 0 }, /* IDSEL 20 - PMCSPAN */
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};
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const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
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irq = PCI_IRQ_TABLE_LOOKUP;
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/* If lookup is zero, always return 0 */
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if (!irq)
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return 0;
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else
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#ifdef CONFIG_MVME5100_IPMC761_PRESENT
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/* If IPMC761 present, return table value */
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return irq;
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#else
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/* If IPMC761 not present, we don't have an i8259 so adjust */
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return (irq - NUM_8259_INTERRUPTS);
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#endif
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}
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static void
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mvme5100_pcibios_fixup_resources(struct pci_dev *dev)
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{
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int i;
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if ((dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
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(dev->device == PCI_DEVICE_ID_MOTOROLA_HAWK))
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for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
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{
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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}
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}
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static void __init
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mvme5100_setup_bridge(void)
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{
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struct pci_controller* hose;
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
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pci_init_resource(&hose->io_resource, MVME5100_PCI_LOWER_IO,
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MVME5100_PCI_UPPER_IO, IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource(&hose->mem_resources[0], MVME5100_PCI_LOWER_MEM,
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MVME5100_PCI_UPPER_MEM, IORESOURCE_MEM,
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"PCI host bridge");
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hose->io_space.start = MVME5100_PCI_LOWER_IO;
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hose->io_space.end = MVME5100_PCI_UPPER_IO;
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hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
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hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
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hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
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/* Use indirect method of Hawk */
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setup_indirect_pci(hose, MVME5100_PCI_CONFIG_ADDR,
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MVME5100_PCI_CONFIG_DATA);
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = mvme5100_map_irq;
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}
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static void __init
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mvme5100_setup_arch(void)
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{
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if ( ppc_md.progress )
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ppc_md.progress("mvme5100_setup_arch: enter", 0);
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loops_per_jiffy = 50000000 / HZ;
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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if ( ppc_md.progress )
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ppc_md.progress("mvme5100_setup_arch: find_bridges", 0);
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/* Setup PCI host bridge */
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mvme5100_setup_bridge();
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/* Find and map our OpenPIC */
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hawk_mpic_init(MVME5100_PCI_MEM_OFFSET);
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OpenPIC_InitSenses = mvme5100_openpic_initsenses;
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OpenPIC_NumInitSenses = sizeof(mvme5100_openpic_initsenses);
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printk("MVME5100 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
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if ( ppc_md.progress )
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ppc_md.progress("mvme5100_setup_arch: exit", 0);
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return;
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}
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static void __init
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mvme5100_init2(void)
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{
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#ifdef CONFIG_MVME5100_IPMC761_PRESENT
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request_region(0x00,0x20,"dma1");
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request_region(0x20,0x20,"pic1");
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request_region(0x40,0x20,"timer");
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request_region(0x80,0x10,"dma page reg");
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request_region(0xa0,0x20,"pic2");
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request_region(0xc0,0x20,"dma2");
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#endif
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return;
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}
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/*
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* Interrupt setup and service.
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* Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC.
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*/
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static void __init
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mvme5100_init_IRQ(void)
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{
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#ifdef CONFIG_MVME5100_IPMC761_PRESENT
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int i;
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#endif
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if ( ppc_md.progress )
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ppc_md.progress("init_irq: enter", 0);
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openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
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#ifdef CONFIG_MVME5100_IPMC761_PRESENT
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openpic_init(NUM_8259_INTERRUPTS);
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openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
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&i8259_irq);
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i8259_init(0, 0);
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#else
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openpic_init(0);
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#endif
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if ( ppc_md.progress )
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ppc_md.progress("init_irq: exit", 0);
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return;
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}
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/*
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* Set BAT 3 to map 0xf0000000 to end of physical memory space.
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*/
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static __inline__ void
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mvme5100_set_bat(void)
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{
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mb();
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mtspr(SPRN_DBAT1U, 0xf0001ffe);
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mtspr(SPRN_DBAT1L, 0xf000002a);
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mb();
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}
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static unsigned long __init
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mvme5100_find_end_of_memory(void)
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{
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return hawk_get_mem_size(MVME5100_HAWK_SMC_BASE);
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}
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static void __init
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mvme5100_map_io(void)
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{
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io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
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ioremap_base = 0xfe000000;
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}
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static void
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mvme5100_reset_board(void)
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{
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local_irq_disable();
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/* Set exception prefix high - to the firmware */
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_nmask_and_or_msr(0, MSR_IP);
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out_8((u_char *)MVME5100_BOARD_MODRST_REG, 0x01);
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return;
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}
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static void
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mvme5100_restart(char *cmd)
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{
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volatile ulong i = 10000000;
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mvme5100_reset_board();
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while (i-- > 0);
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panic("restart failed\n");
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}
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static void
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mvme5100_halt(void)
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{
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local_irq_disable();
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while (1);
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}
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static void
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mvme5100_power_off(void)
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{
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mvme5100_halt();
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}
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static int
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mvme5100_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: Motorola\n");
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seq_printf(m, "machine\t\t: MVME5100\n");
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return 0;
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}
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TODC_ALLOC();
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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mvme5100_set_bat();
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isa_io_base = MVME5100_ISA_IO_BASE;
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isa_mem_base = MVME5100_ISA_MEM_BASE;
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pci_dram_offset = MVME5100_PCI_DRAM_OFFSET;
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ppc_md.setup_arch = mvme5100_setup_arch;
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ppc_md.show_cpuinfo = mvme5100_show_cpuinfo;
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ppc_md.init_IRQ = mvme5100_init_IRQ;
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ppc_md.get_irq = openpic_get_irq;
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ppc_md.init = mvme5100_init2;
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ppc_md.restart = mvme5100_restart;
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ppc_md.power_off = mvme5100_power_off;
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ppc_md.halt = mvme5100_halt;
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ppc_md.find_end_of_memory = mvme5100_find_end_of_memory;
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ppc_md.setup_io_mappings = mvme5100_map_io;
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TODC_INIT(TODC_TYPE_MK48T37, MVME5100_NVRAM_AS0, MVME5100_NVRAM_AS1,
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MVME5100_NVRAM_DATA, 8);
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.calibrate_decr = todc_calibrate_decr;
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ppc_md.nvram_read_val = todc_m48txx_read_val;
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ppc_md.nvram_write_val = todc_m48txx_write_val;
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}
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