e00c9a0c2e
This problem belongs to the core synchronization issues. The cpu1 already updated spin_table values, but bootcore cannot get this value in time. After bootcpu hibiernation restore the pages. we are now running with the kernel data of the old kernel fully restored. if we reset the non-bootcpus that will be reset cache(tlb), the non-bootcpus will get new address(map virtual and physical address spaces). but bootcpu tlb cache still use boot kernel data, so we need to invalidate the bootcpu tlb cache make it to get new main memory data. log: Enabling non-boot CPUs ... smp_85xx_kick_cpu: timeout waiting for core 1 to reset smp: failed starting cpu 1 (rc -2) Error taking CPU1 up: -2 Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: Anton Vorontsov <anton@enomsg.org> [scottwood@freescale.com: reworded code comment for clarity] Signed-off-by: Scott Wood <scottwood@freescale.com>
202 lines
3.6 KiB
ArmAsm
202 lines
3.6 KiB
ArmAsm
/*
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* Based on swsusp_32.S, modified for FSL BookE by
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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* Copyright (c) 2009-2010 MontaVista Software, LLC.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mmu.h>
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/*
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* Structure for storing CPU registers on the save area.
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*/
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#define SL_SP 0
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#define SL_PC 4
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#define SL_MSR 8
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#define SL_TCR 0xc
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#define SL_SPRG0 0x10
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#define SL_SPRG1 0x14
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#define SL_SPRG2 0x18
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#define SL_SPRG3 0x1c
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#define SL_SPRG4 0x20
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#define SL_SPRG5 0x24
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#define SL_SPRG6 0x28
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#define SL_SPRG7 0x2c
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#define SL_TBU 0x30
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#define SL_TBL 0x34
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#define SL_R2 0x38
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#define SL_CR 0x3c
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#define SL_LR 0x40
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#define SL_R12 0x44 /* r12 to r31 */
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#define SL_SIZE (SL_R12 + 80)
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.section .data
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.align 5
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_GLOBAL(swsusp_save_area)
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.space SL_SIZE
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.section .text
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.align 5
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_GLOBAL(swsusp_arch_suspend)
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lis r11,swsusp_save_area@h
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ori r11,r11,swsusp_save_area@l
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mflr r0
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stw r0,SL_LR(r11)
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mfcr r0
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stw r0,SL_CR(r11)
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stw r1,SL_SP(r11)
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stw r2,SL_R2(r11)
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stmw r12,SL_R12(r11)
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/* Save MSR & TCR */
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mfmsr r4
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stw r4,SL_MSR(r11)
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mfspr r4,SPRN_TCR
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stw r4,SL_TCR(r11)
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/* Get a stable timebase and save it */
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1: mfspr r4,SPRN_TBRU
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stw r4,SL_TBU(r11)
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mfspr r5,SPRN_TBRL
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stw r5,SL_TBL(r11)
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mfspr r3,SPRN_TBRU
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cmpw r3,r4
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bne 1b
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/* Save SPRGs */
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mfsprg r4,0
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stw r4,SL_SPRG0(r11)
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mfsprg r4,1
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stw r4,SL_SPRG1(r11)
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mfsprg r4,2
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stw r4,SL_SPRG2(r11)
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mfsprg r4,3
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stw r4,SL_SPRG3(r11)
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mfsprg r4,4
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stw r4,SL_SPRG4(r11)
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mfsprg r4,5
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stw r4,SL_SPRG5(r11)
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mfsprg r4,6
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stw r4,SL_SPRG6(r11)
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mfsprg r4,7
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stw r4,SL_SPRG7(r11)
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/* Call the low level suspend stuff (we should probably have made
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* a stackframe...
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*/
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bl swsusp_save
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/* Restore LR from the save area */
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lis r11,swsusp_save_area@h
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ori r11,r11,swsusp_save_area@l
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lwz r0,SL_LR(r11)
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mtlr r0
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blr
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_GLOBAL(swsusp_arch_resume)
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sync
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/* Load ptr the list of pages to copy in r3 */
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lis r11,(restore_pblist)@h
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ori r11,r11,restore_pblist@l
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lwz r3,0(r11)
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/* Copy the pages. This is a very basic implementation, to
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* be replaced by something more cache efficient */
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1:
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li r0,256
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mtctr r0
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lwz r5,pbe_address(r3) /* source */
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lwz r6,pbe_orig_address(r3) /* destination */
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2:
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lwz r8,0(r5)
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lwz r9,4(r5)
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lwz r10,8(r5)
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lwz r11,12(r5)
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addi r5,r5,16
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stw r8,0(r6)
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stw r9,4(r6)
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stw r10,8(r6)
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stw r11,12(r6)
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addi r6,r6,16
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bdnz 2b
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lwz r3,pbe_next(r3)
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cmpwi 0,r3,0
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bne 1b
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bl flush_dcache_L1
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bl flush_instruction_cache
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lis r11,swsusp_save_area@h
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ori r11,r11,swsusp_save_area@l
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/*
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* Mappings from virtual addresses to physical addresses may be
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* different than they were prior to restoring hibernation state.
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* Invalidate the TLB so that the boot CPU is using the new
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* mappings.
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*/
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bl _tlbil_all
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lwz r4,SL_SPRG0(r11)
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mtsprg 0,r4
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lwz r4,SL_SPRG1(r11)
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mtsprg 1,r4
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lwz r4,SL_SPRG2(r11)
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mtsprg 2,r4
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lwz r4,SL_SPRG3(r11)
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mtsprg 3,r4
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lwz r4,SL_SPRG4(r11)
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mtsprg 4,r4
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lwz r4,SL_SPRG5(r11)
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mtsprg 5,r4
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lwz r4,SL_SPRG6(r11)
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mtsprg 6,r4
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lwz r4,SL_SPRG7(r11)
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mtsprg 7,r4
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/* restore the MSR */
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lwz r3,SL_MSR(r11)
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mtmsr r3
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/* Restore TB */
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li r3,0
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mtspr SPRN_TBWL,r3
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lwz r3,SL_TBU(r11)
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lwz r4,SL_TBL(r11)
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mtspr SPRN_TBWU,r3
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mtspr SPRN_TBWL,r4
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/* Restore TCR and clear any pending bits in TSR. */
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lwz r4,SL_TCR(r11)
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mtspr SPRN_TCR,r4
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lis r4, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
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mtspr SPRN_TSR,r4
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/* Kick decrementer */
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li r0,1
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mtdec r0
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/* Restore the callee-saved registers and return */
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lwz r0,SL_CR(r11)
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mtcr r0
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lwz r2,SL_R2(r11)
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lmw r12,SL_R12(r11)
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lwz r1,SL_SP(r11)
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lwz r0,SL_LR(r11)
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mtlr r0
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li r3,0
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blr
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