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Mike Looijmans 9e9a615103 zynq-fpga: Only route PR via PCAP when required 
The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
it impossible to use the ICAP interface for partial reconfiguration.

This patch changes the driver to only activate PR over PCAP while the
device is actively being accessed by the driver for programming.

This allows both PCAP and ICAP interfaces to be used for PR.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 		2018-11-11 12:58:27 -08:00
..
Kconfig fpga: dfl: add FPGA Accelerated Function Unit driver basic framework 2018-07-15 13:55:46 +02:00
Makefile fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support 2018-07-15 13:55:47 +02:00
altera-cvp.c fpga: altera-cvp: Fix registration for CvP incapable devices 2018-11-11 12:58:27 -08:00
altera-fpga2sdram.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
altera-freeze-bridge.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
altera-hps2fpga.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
altera-pr-ip-core-plat.c fpga: use SPDX 2018-05-25 18:23:56 +02:00
altera-pr-ip-core.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
altera-ps-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
dfl-afu-dma-region.c drivers: fpga: fix two trivial spelling mistakes 2018-09-12 09:43:53 +02:00
dfl-afu-main.c fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support 2018-07-15 13:55:47 +02:00
dfl-afu-region.c fpga: dfl: afu: add afu sub feature support 2018-07-15 13:55:47 +02:00
dfl-afu.h fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support 2018-07-15 13:55:47 +02:00
dfl-fme-br.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
dfl-fme-main.c fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme-mgr.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
dfl-fme-pr.c fpga: dfl: fme: remove set but not used variable 'priv' 2018-11-11 12:58:27 -08:00
dfl-fme-pr.h fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-fme-region.c fpga: add devm_fpga_region_create 2018-10-16 11:13:50 +02:00
dfl-fme.h fpga: dfl: fme: add partial reconfiguration sub feature support 2018-07-15 13:55:46 +02:00
dfl-pci.c fpga: dfl-pci: add enumeration for feature devices 2018-07-15 13:55:45 +02:00
dfl.c fpga: add devm_fpga_region_create 2018-10-16 11:13:50 +02:00
dfl.h fpga: dfl: add dfl_fpga_check_port_id function. 2018-07-15 13:55:45 +02:00
fpga-bridge.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
fpga-mgr.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
fpga-region.c fpga: add devm_fpga_region_create 2018-10-16 11:13:50 +02:00
ice40-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
machxo2-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
of-fpga-region.c fpga: add devm_fpga_region_create 2018-10-16 11:13:50 +02:00
socfpga-a10.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
socfpga.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
ts73xx-fpga.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
xilinx-pr-decoupler.c fpga: bridge: add devm_fpga_bridge_create 2018-10-16 11:13:50 +02:00
xilinx-spi.c fpga: mgr: add devm_fpga_mgr_create 2018-10-16 11:13:50 +02:00
zynq-fpga.c zynq-fpga: Only route PR via PCAP when required 2018-11-11 12:58:27 -08:00