497 lines
15 KiB
C
497 lines
15 KiB
C
/*
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* Network device driver for Cell Processor-Based Blade and Celleb platform
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*
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* (C) Copyright IBM Corp. 2005
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* (C) Copyright 2006 TOSHIBA CORPORATION
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*
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* Authors : Utz Bacher <utz.bacher@de.ibm.com>
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* Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _SPIDER_NET_H
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#define _SPIDER_NET_H
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#define VERSION "2.0 B"
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#include "sungem_phy.h"
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extern int spider_net_stop(struct net_device *netdev);
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extern int spider_net_open(struct net_device *netdev);
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extern const struct ethtool_ops spider_net_ethtool_ops;
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extern char spider_net_driver_name[];
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#define SPIDER_NET_MAX_FRAME 2312
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#define SPIDER_NET_MAX_MTU 2294
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#define SPIDER_NET_MIN_MTU 64
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#define SPIDER_NET_RXBUF_ALIGN 128
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#define SPIDER_NET_RX_DESCRIPTORS_DEFAULT 256
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#define SPIDER_NET_RX_DESCRIPTORS_MIN 16
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#define SPIDER_NET_RX_DESCRIPTORS_MAX 512
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#define SPIDER_NET_TX_DESCRIPTORS_DEFAULT 256
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#define SPIDER_NET_TX_DESCRIPTORS_MIN 16
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#define SPIDER_NET_TX_DESCRIPTORS_MAX 512
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#define SPIDER_NET_TX_TIMER (HZ/5)
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#define SPIDER_NET_ANEG_TIMER (HZ)
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#define SPIDER_NET_ANEG_TIMEOUT 5
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#define SPIDER_NET_RX_CSUM_DEFAULT 1
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#define SPIDER_NET_WATCHDOG_TIMEOUT 50*HZ
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#define SPIDER_NET_NAPI_WEIGHT 64
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#define SPIDER_NET_FIRMWARE_SEQS 6
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#define SPIDER_NET_FIRMWARE_SEQWORDS 1024
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#define SPIDER_NET_FIRMWARE_LEN (SPIDER_NET_FIRMWARE_SEQS * \
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SPIDER_NET_FIRMWARE_SEQWORDS * \
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sizeof(u32))
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#define SPIDER_NET_FIRMWARE_NAME "spider_fw.bin"
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/** spider_net SMMIO registers */
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#define SPIDER_NET_GHIINT0STS 0x00000000
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#define SPIDER_NET_GHIINT1STS 0x00000004
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#define SPIDER_NET_GHIINT2STS 0x00000008
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#define SPIDER_NET_GHIINT0MSK 0x00000010
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#define SPIDER_NET_GHIINT1MSK 0x00000014
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#define SPIDER_NET_GHIINT2MSK 0x00000018
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#define SPIDER_NET_GRESUMINTNUM 0x00000020
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#define SPIDER_NET_GREINTNUM 0x00000024
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#define SPIDER_NET_GFFRMNUM 0x00000028
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#define SPIDER_NET_GFAFRMNUM 0x0000002c
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#define SPIDER_NET_GFBFRMNUM 0x00000030
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#define SPIDER_NET_GFCFRMNUM 0x00000034
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#define SPIDER_NET_GFDFRMNUM 0x00000038
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/* clear them (don't use it) */
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#define SPIDER_NET_GFREECNNUM 0x0000003c
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#define SPIDER_NET_GONETIMENUM 0x00000040
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#define SPIDER_NET_GTOUTFRMNUM 0x00000044
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#define SPIDER_NET_GTXMDSET 0x00000050
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#define SPIDER_NET_GPCCTRL 0x00000054
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#define SPIDER_NET_GRXMDSET 0x00000058
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#define SPIDER_NET_GIPSECINIT 0x0000005c
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#define SPIDER_NET_GFTRESTRT 0x00000060
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#define SPIDER_NET_GRXDMAEN 0x00000064
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#define SPIDER_NET_GMRWOLCTRL 0x00000068
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#define SPIDER_NET_GPCWOPCMD 0x0000006c
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#define SPIDER_NET_GPCROPCMD 0x00000070
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#define SPIDER_NET_GTTFRMCNT 0x00000078
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#define SPIDER_NET_GTESTMD 0x0000007c
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#define SPIDER_NET_GSINIT 0x00000080
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#define SPIDER_NET_GSnPRGADR 0x00000084
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#define SPIDER_NET_GSnPRGDAT 0x00000088
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#define SPIDER_NET_GMACOPEMD 0x00000100
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#define SPIDER_NET_GMACLENLMT 0x00000108
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#define SPIDER_NET_GMACST 0x00000110
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#define SPIDER_NET_GMACINTEN 0x00000118
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#define SPIDER_NET_GMACPHYCTRL 0x00000120
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#define SPIDER_NET_GMACAPAUSE 0x00000154
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#define SPIDER_NET_GMACTXPAUSE 0x00000164
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#define SPIDER_NET_GMACMODE 0x000001b0
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#define SPIDER_NET_GMACBSTLMT 0x000001b4
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#define SPIDER_NET_GMACUNIMACU 0x000001c0
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#define SPIDER_NET_GMACUNIMACL 0x000001c8
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#define SPIDER_NET_GMRMHFILnR 0x00000400
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#define SPIDER_NET_MULTICAST_HASHES 256
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#define SPIDER_NET_GMRUAFILnR 0x00000500
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#define SPIDER_NET_GMRUA0FIL15R 0x00000578
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#define SPIDER_NET_GTTQMSK 0x00000934
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/* RX DMA controller registers, all 0x00000a.. are for DMA controller A,
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* 0x00000b.. for DMA controller B, etc. */
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#define SPIDER_NET_GDADCHA 0x00000a00
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#define SPIDER_NET_GDADMACCNTR 0x00000a04
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#define SPIDER_NET_GDACTDPA 0x00000a08
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#define SPIDER_NET_GDACTDCNT 0x00000a0c
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#define SPIDER_NET_GDACDBADDR 0x00000a20
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#define SPIDER_NET_GDACDBSIZE 0x00000a24
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#define SPIDER_NET_GDACNEXTDA 0x00000a28
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#define SPIDER_NET_GDACCOMST 0x00000a2c
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#define SPIDER_NET_GDAWBCOMST 0x00000a30
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#define SPIDER_NET_GDAWBRSIZE 0x00000a34
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#define SPIDER_NET_GDAWBVSIZE 0x00000a38
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#define SPIDER_NET_GDAWBTRST 0x00000a3c
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#define SPIDER_NET_GDAWBTRERR 0x00000a40
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/* TX DMA controller registers */
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#define SPIDER_NET_GDTDCHA 0x00000e00
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#define SPIDER_NET_GDTDMACCNTR 0x00000e04
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#define SPIDER_NET_GDTCDPA 0x00000e08
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#define SPIDER_NET_GDTDMASEL 0x00000e14
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#define SPIDER_NET_ECMODE 0x00000f00
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/* clock and reset control register */
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#define SPIDER_NET_CKRCTRL 0x00000ff0
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/** SCONFIG registers */
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#define SPIDER_NET_SCONFIG_IOACTE 0x00002810
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/** interrupt mask registers */
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#define SPIDER_NET_INT0_MASK_VALUE 0x3f7fe2c7
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#define SPIDER_NET_INT1_MASK_VALUE 0x0000fff2
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#define SPIDER_NET_INT2_MASK_VALUE 0x000003f1
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/* we rely on flagged descriptor interrupts */
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#define SPIDER_NET_FRAMENUM_VALUE 0x00000000
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/* set this first, then the FRAMENUM_VALUE */
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#define SPIDER_NET_GFXFRAMES_VALUE 0x00000000
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#define SPIDER_NET_STOP_SEQ_VALUE 0x00000000
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#define SPIDER_NET_RUN_SEQ_VALUE 0x0000007e
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#define SPIDER_NET_PHY_CTRL_VALUE 0x00040040
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/* #define SPIDER_NET_PHY_CTRL_VALUE 0x01070080*/
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#define SPIDER_NET_RXMODE_VALUE 0x00000011
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/* auto retransmission in case of MAC aborts */
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#define SPIDER_NET_TXMODE_VALUE 0x00010000
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#define SPIDER_NET_RESTART_VALUE 0x00000000
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#define SPIDER_NET_WOL_VALUE 0x00001111
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#if 0
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#define SPIDER_NET_WOL_VALUE 0x00000000
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#endif
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#define SPIDER_NET_IPSECINIT_VALUE 0x6f716f71
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/* pause frames: automatic, no upper retransmission count */
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/* outside loopback mode: ETOMOD signal dont matter, not connected */
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/* ETOMOD signal is brought to PHY reset. bit 2 must be 1 in Celleb */
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#define SPIDER_NET_OPMODE_VALUE 0x00000067
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/*#define SPIDER_NET_OPMODE_VALUE 0x001b0062*/
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#define SPIDER_NET_LENLMT_VALUE 0x00000908
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#define SPIDER_NET_MACAPAUSE_VALUE 0x00000800 /* about 1 ms */
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#define SPIDER_NET_TXPAUSE_VALUE 0x00000000
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#define SPIDER_NET_MACMODE_VALUE 0x00000001
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#define SPIDER_NET_BURSTLMT_VALUE 0x00000200 /* about 16 us */
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/* DMAC control register GDMACCNTR
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*
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* 1(0) enable r/tx dma
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* 0000000 fixed to 0
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*
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* 000000 fixed to 0
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* 0(1) en/disable descr writeback on force end
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* 0(1) force end
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*
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* 000000 fixed to 0
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* 00 burst alignment: 128 bytes
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* 11 burst alignment: 1024 bytes
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*
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* 00000 fixed to 0
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* 0 descr writeback size 32 bytes
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* 0(1) descr chain end interrupt enable
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* 0(1) descr status writeback enable */
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/* to set RX_DMA_EN */
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#define SPIDER_NET_DMA_RX_VALUE 0x80000000
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#define SPIDER_NET_DMA_RX_FEND_VALUE 0x00030003
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/* to set TX_DMA_EN */
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#define SPIDER_NET_TX_DMA_EN 0x80000000
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#define SPIDER_NET_GDTBSTA 0x00000300
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#define SPIDER_NET_GDTDCEIDIS 0x00000002
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#define SPIDER_NET_DMA_TX_VALUE SPIDER_NET_TX_DMA_EN | \
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SPIDER_NET_GDTDCEIDIS | \
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SPIDER_NET_GDTBSTA
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#define SPIDER_NET_DMA_TX_FEND_VALUE 0x00030003
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/* SPIDER_NET_UA_DESCR_VALUE is OR'ed with the unicast address */
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#define SPIDER_NET_UA_DESCR_VALUE 0x00080000
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#define SPIDER_NET_PROMISC_VALUE 0x00080000
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#define SPIDER_NET_NONPROMISC_VALUE 0x00000000
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#define SPIDER_NET_DMASEL_VALUE 0x00000001
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#define SPIDER_NET_ECMODE_VALUE 0x00000000
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#define SPIDER_NET_CKRCTRL_RUN_VALUE 0x1fff010f
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#define SPIDER_NET_CKRCTRL_STOP_VALUE 0x0000010f
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#define SPIDER_NET_SBIMSTATE_VALUE 0x00000000
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#define SPIDER_NET_SBTMSTATE_VALUE 0x00000000
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/* SPIDER_NET_GHIINT0STS bits, in reverse order so that they can be used
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* with 1 << SPIDER_NET_... */
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enum spider_net_int0_status {
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SPIDER_NET_GPHYINT = 0,
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SPIDER_NET_GMAC2INT,
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SPIDER_NET_GMAC1INT,
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SPIDER_NET_GIPSINT,
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SPIDER_NET_GFIFOINT,
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SPIDER_NET_GDMACINT,
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SPIDER_NET_GSYSINT,
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SPIDER_NET_GPWOPCMPINT,
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SPIDER_NET_GPROPCMPINT,
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SPIDER_NET_GPWFFINT,
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SPIDER_NET_GRMDADRINT,
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SPIDER_NET_GRMARPINT,
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SPIDER_NET_GRMMPINT,
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SPIDER_NET_GDTDEN0INT,
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SPIDER_NET_GDDDEN0INT,
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SPIDER_NET_GDCDEN0INT,
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SPIDER_NET_GDBDEN0INT,
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SPIDER_NET_GDADEN0INT,
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SPIDER_NET_GDTFDCINT,
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SPIDER_NET_GDDFDCINT,
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SPIDER_NET_GDCFDCINT,
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SPIDER_NET_GDBFDCINT,
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SPIDER_NET_GDAFDCINT,
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SPIDER_NET_GTTEDINT,
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SPIDER_NET_GDTDCEINT,
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SPIDER_NET_GRFDNMINT,
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SPIDER_NET_GRFCNMINT,
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SPIDER_NET_GRFBNMINT,
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SPIDER_NET_GRFANMINT,
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SPIDER_NET_GRFNMINT,
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SPIDER_NET_G1TMCNTINT,
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SPIDER_NET_GFREECNTINT
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};
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/* GHIINT1STS bits */
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enum spider_net_int1_status {
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SPIDER_NET_GTMFLLINT = 0,
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SPIDER_NET_GRMFLLINT,
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SPIDER_NET_GTMSHTINT,
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SPIDER_NET_GDTINVDINT,
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SPIDER_NET_GRFDFLLINT,
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SPIDER_NET_GDDDCEINT,
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SPIDER_NET_GDDINVDINT,
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SPIDER_NET_GRFCFLLINT,
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SPIDER_NET_GDCDCEINT,
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SPIDER_NET_GDCINVDINT,
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SPIDER_NET_GRFBFLLINT,
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SPIDER_NET_GDBDCEINT,
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SPIDER_NET_GDBINVDINT,
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SPIDER_NET_GRFAFLLINT,
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SPIDER_NET_GDADCEINT,
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SPIDER_NET_GDAINVDINT,
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SPIDER_NET_GDTRSERINT,
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SPIDER_NET_GDDRSERINT,
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SPIDER_NET_GDCRSERINT,
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SPIDER_NET_GDBRSERINT,
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SPIDER_NET_GDARSERINT,
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SPIDER_NET_GDSERINT,
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SPIDER_NET_GDTPTERINT,
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SPIDER_NET_GDDPTERINT,
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SPIDER_NET_GDCPTERINT,
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SPIDER_NET_GDBPTERINT,
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SPIDER_NET_GDAPTERINT
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};
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/* GHIINT2STS bits */
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enum spider_net_int2_status {
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SPIDER_NET_GPROPERINT = 0,
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SPIDER_NET_GMCTCRSNGINT,
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SPIDER_NET_GMCTLCOLINT,
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SPIDER_NET_GMCTTMOTINT,
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SPIDER_NET_GMCRCAERINT,
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SPIDER_NET_GMCRCALERINT,
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SPIDER_NET_GMCRALNERINT,
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SPIDER_NET_GMCROVRINT,
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SPIDER_NET_GMCRRNTINT,
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SPIDER_NET_GMCRRXERINT,
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SPIDER_NET_GTITCSERINT,
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SPIDER_NET_GTIFMTERINT,
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SPIDER_NET_GTIPKTRVKINT,
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SPIDER_NET_GTISPINGINT,
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SPIDER_NET_GTISADNGINT,
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SPIDER_NET_GTISPDNGINT,
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SPIDER_NET_GRIFMTERINT,
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SPIDER_NET_GRIPKTRVKINT,
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SPIDER_NET_GRISPINGINT,
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SPIDER_NET_GRISADNGINT,
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SPIDER_NET_GRISPDNGINT
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};
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#define SPIDER_NET_TXINT (1 << SPIDER_NET_GDTFDCINT)
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/* We rely on flagged descriptor interrupts */
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#define SPIDER_NET_RXINT ( (1 << SPIDER_NET_GDAFDCINT) )
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#define SPIDER_NET_LINKINT ( 1 << SPIDER_NET_GMAC2INT )
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#define SPIDER_NET_ERRINT ( 0xffffffff & \
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(~SPIDER_NET_TXINT) & \
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(~SPIDER_NET_RXINT) & \
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(~SPIDER_NET_LINKINT) )
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#define SPIDER_NET_GPREXEC 0x80000000
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#define SPIDER_NET_GPRDAT_MASK 0x0000ffff
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#define SPIDER_NET_DMAC_NOINTR_COMPLETE 0x00800000
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#define SPIDER_NET_DMAC_TXFRMTL 0x00040000
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#define SPIDER_NET_DMAC_TCP 0x00020000
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#define SPIDER_NET_DMAC_UDP 0x00030000
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#define SPIDER_NET_TXDCEST 0x08000000
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#define SPIDER_NET_DESCR_RXFDIS 0x00000001
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#define SPIDER_NET_DESCR_RXDCEIS 0x00000002
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#define SPIDER_NET_DESCR_RXDEN0IS 0x00000004
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#define SPIDER_NET_DESCR_RXINVDIS 0x00000008
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#define SPIDER_NET_DESCR_RXRERRIS 0x00000010
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#define SPIDER_NET_DESCR_RXFDCIMS 0x00000100
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#define SPIDER_NET_DESCR_RXDCEIMS 0x00000200
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#define SPIDER_NET_DESCR_RXDEN0IMS 0x00000400
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#define SPIDER_NET_DESCR_RXINVDIMS 0x00000800
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#define SPIDER_NET_DESCR_RXRERRMIS 0x00001000
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#define SPIDER_NET_DESCR_UNUSED 0x077fe0e0
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#define SPIDER_NET_DESCR_IND_PROC_MASK 0xF0000000
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#define SPIDER_NET_DESCR_COMPLETE 0x00000000 /* used in rx and tx */
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#define SPIDER_NET_DESCR_RESPONSE_ERROR 0x10000000 /* used in rx and tx */
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#define SPIDER_NET_DESCR_PROTECTION_ERROR 0x20000000 /* used in rx and tx */
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#define SPIDER_NET_DESCR_FRAME_END 0x40000000 /* used in rx */
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#define SPIDER_NET_DESCR_FORCE_END 0x50000000 /* used in rx and tx */
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#define SPIDER_NET_DESCR_CARDOWNED 0xA0000000 /* used in rx and tx */
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#define SPIDER_NET_DESCR_NOT_IN_USE 0xF0000000
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#define SPIDER_NET_DESCR_TXDESFLG 0x00800000
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#define SPIDER_NET_DESCR_BAD_STATUS (SPIDER_NET_DESCR_RXDEN0IS | \
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SPIDER_NET_DESCR_RXRERRIS | \
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SPIDER_NET_DESCR_RXDEN0IMS | \
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SPIDER_NET_DESCR_RXINVDIMS | \
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SPIDER_NET_DESCR_RXRERRMIS | \
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SPIDER_NET_DESCR_UNUSED)
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/* Descriptor, as defined by the hardware */
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struct spider_net_hw_descr {
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u32 buf_addr;
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u32 buf_size;
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u32 next_descr_addr;
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u32 dmac_cmd_status;
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u32 result_size;
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u32 valid_size; /* all zeroes for tx */
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u32 data_status;
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u32 data_error; /* all zeroes for tx */
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} __attribute__((aligned(32)));
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struct spider_net_descr {
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struct spider_net_hw_descr *hwdescr;
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struct sk_buff *skb;
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u32 bus_addr;
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struct spider_net_descr *next;
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struct spider_net_descr *prev;
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};
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struct spider_net_descr_chain {
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spinlock_t lock;
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struct spider_net_descr *head;
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struct spider_net_descr *tail;
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struct spider_net_descr *ring;
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int num_desc;
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struct spider_net_hw_descr *hwring;
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dma_addr_t dma_addr;
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};
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/* descriptor data_status bits */
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#define SPIDER_NET_RX_IPCHK 29
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#define SPIDER_NET_RX_TCPCHK 28
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#define SPIDER_NET_VLAN_PACKET 21
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#define SPIDER_NET_DATA_STATUS_CKSUM_MASK ( (1 << SPIDER_NET_RX_IPCHK) | \
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(1 << SPIDER_NET_RX_TCPCHK) )
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/* descriptor data_error bits */
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#define SPIDER_NET_RX_IPCHKERR 27
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#define SPIDER_NET_RX_RXTCPCHKERR 28
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#define SPIDER_NET_DATA_ERR_CKSUM_MASK (1 << SPIDER_NET_RX_IPCHKERR)
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/* the cases we don't pass the packet to the stack.
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* 701b8000 would be correct, but every packets gets that flag */
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#define SPIDER_NET_DESTROY_RX_FLAGS 0x700b8000
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/* this will be bigger some time */
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struct spider_net_options {
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int rx_csum; /* for rx: if 0 ip_summed=NONE,
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if 1 and hw has verified, ip_summed=UNNECESSARY */
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};
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#define SPIDER_NET_DEFAULT_MSG ( NETIF_MSG_DRV | \
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NETIF_MSG_PROBE | \
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NETIF_MSG_LINK | \
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NETIF_MSG_TIMER | \
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NETIF_MSG_IFDOWN | \
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NETIF_MSG_IFUP | \
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NETIF_MSG_RX_ERR | \
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NETIF_MSG_TX_ERR | \
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NETIF_MSG_TX_QUEUED | \
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NETIF_MSG_INTR | \
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NETIF_MSG_TX_DONE | \
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NETIF_MSG_RX_STATUS | \
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NETIF_MSG_PKTDATA | \
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NETIF_MSG_HW | \
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NETIF_MSG_WOL )
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struct spider_net_extra_stats {
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unsigned long rx_desc_error;
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unsigned long tx_timeouts;
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unsigned long alloc_rx_skb_error;
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unsigned long rx_iommu_map_error;
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unsigned long tx_iommu_map_error;
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unsigned long rx_desc_unk_state;
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};
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struct spider_net_card {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct mii_phy phy;
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struct napi_struct napi;
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int medium;
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void __iomem *regs;
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struct spider_net_descr_chain tx_chain;
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struct spider_net_descr_chain rx_chain;
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struct spider_net_descr *low_watermark;
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int aneg_count;
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struct timer_list aneg_timer;
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struct timer_list tx_timer;
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struct work_struct tx_timeout_task;
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atomic_t tx_timeout_task_counter;
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wait_queue_head_t waitq;
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int num_rx_ints;
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int ignore_rx_ramfull;
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/* for ethtool */
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int msg_enable;
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struct spider_net_extra_stats spider_stats;
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struct spider_net_options options;
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/* Must be last item in struct */
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struct spider_net_descr darray[0];
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};
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#endif
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