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Martin Blumenstingl 7377ba16b5 clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers 
[ Upstream commit a29ae8600d ]

Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers.
In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when
booting Linux the PLL fails to lock.
The initialization sequence from u-boot is:
- put the PLL into reset
- write 0x59C88000 to HHI_GP_PLL_CNTL2
- write 0xCA463823 to HHI_GP_PLL_CNTL3
- write 0x0286A027 to HHI_GP_PLL_CNTL4
- write 0x00003000 to HHI_GP_PLL_CNTL5
- set M, N, OD and the enable bit
- take the PLL out of reset
- check if it has locked
- disable the PLL

In Linux we already initialize M, N, OD, the enable and the reset bits.
Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the
exact meaning is unknown) so the PLL can lock when the vendor u-boot did
not initialize these registers yet.

Fixes: b882964b37 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
 		2020-06-24 17:50:23 +02:00
..
Kconfig
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Makefile
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axg-aoclk.c
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axg-aoclk.h
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axg-audio.c
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axg-audio.h
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axg.c
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axg.h
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clk-cpu-dyndiv.c
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clk-cpu-dyndiv.h
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clk-dualdiv.c
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clk-dualdiv.h
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clk-mpll.c
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clk-mpll.h
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clk-phase.c
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clk-phase.h
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clk-pll.c clk: meson: pll: Fix by 0 division in __pll_params_to_rate() 2020-02-24 08:36:23 +01:00
clk-pll.h
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clk-regmap.c
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clk-regmap.h
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g12a-aoclk.c
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g12a-aoclk.h
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g12a.c
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g12a.h
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gxbb-aoclk.c
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gxbb-aoclk.h
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gxbb.c
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gxbb.h
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meson-aoclk.c
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meson-aoclk.h
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meson-eeclk.c
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meson-eeclk.h
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meson8b.c clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers 2020-06-24 17:50:23 +02:00
meson8b.h clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers 2020-06-24 17:50:23 +02:00
parm.h
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sclk-div.c
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sclk-div.h
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vid-pll-div.c
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vid-pll-div.h
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