linux/drivers/clk/mmp
Lubomir Rintel aab165d61c clk: mmp2: Fix the order of timer mux parents
[ Upstream commit 8bea5ac0fb ]

Determined empirically, no documentation is available.

The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee43 ("ARM: mmp/mmp2: dt: enable the clock")'

Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-02-05 21:22:43 +00:00
..
Makefile
clk-apbc.c
clk-apmu.c
clk-frac.c clk: mmp: frac: Remove set but not used variable 'prev_rate' 2019-06-07 11:54:48 -07:00
clk-gate.c clk: Remove CLK_IS_BASIC clk flag 2019-04-26 10:40:49 -07:00
clk-mix.c
clk-mmp2.c
clk-of-mmp2.c clk: mmp2: Fix the order of timer mux parents 2020-02-05 21:22:43 +00:00
clk-of-pxa168.c
clk-of-pxa910.c
clk-of-pxa1928.c
clk-pxa168.c
clk-pxa910.c
clk.c clk: mmp: Off by one in mmp_clk_add() 2018-12-03 09:54:48 -08:00
clk.h
reset.c
reset.h