linux/arch/mips/ralink
John Crispin 7e5873d375 MIPS: pci: Add MT7620a PCIE driver
The "a" version of the MT7620 has single port PCIE bus. The driver is
straightforward without any special magic required. The driver works on
MT7620 and MT7628. There are a few magic values that get written to the
pcie phy and a register of which we only know the name. I marked these
places as vodoo in the comments above the code.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11996/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-20 00:39:20 +01:00
..
bootrom.c
cevt-rt3352.c MIPS: ralink: Fix invalid tick count 2015-11-11 08:38:04 +01:00
clk.c clocksource: cosmetic: Drop OF 'dependency' from symbols 2015-10-01 02:18:39 +02:00
common.h
early_printk.c MIPS: ralink: Add tty detection 2015-11-11 08:38:03 +01:00
ill_acc.c
irq-gic.c MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
irq.c genirq: Remove irq argument from irq flow handlers 2015-09-16 15:47:51 +02:00
Kconfig MIPS: pci: Add MT7620a PCIE driver 2016-01-20 00:39:20 +01:00
Makefile MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
mt7620.c MIPS: ralink: Add a few missing clocks 2016-01-20 00:39:20 +01:00
mt7621.c MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
of.c MIPS: Make MIPS_CMDLINE_DTB default 2015-11-11 08:38:37 +01:00
Platform MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
prom.c MIPS: ralink: Unify SoC id handling 2015-11-11 08:37:56 +01:00
reset.c MIPS: ralink: Put the pci bus into reset state before rebooting the SoC 2015-11-11 08:38:14 +01:00
rt288x.c MIPS: ralink: Fix invalid assignment of SoC type 2016-01-20 00:39:20 +01:00
rt305x.c MIPS: ralink: Add a few missing clocks 2016-01-20 00:39:20 +01:00
rt3883.c MIPS: ralink: Add a few missing clocks 2016-01-20 00:39:20 +01:00
timer-gic.c MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
timer.c