560 lines
15 KiB
C
560 lines
15 KiB
C
#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/cpufeature.h>
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#include <linux/bitops.h> /* for LOCK_PREFIX */
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#ifdef __KERNEL__
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struct task_struct; /* one of the stranger aspects of C forward declarations.. */
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extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
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/*
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* Saving eflags is important. It switches not only IOPL between tasks,
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* it also protects other tasks from NT leaking through sysenter etc.
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*/
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#define switch_to(prev,next,last) do { \
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unsigned long esi,edi; \
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asm volatile("pushfl\n\t" /* Save flags */ \
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"pushl %%ebp\n\t" \
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"movl %%esp,%0\n\t" /* save ESP */ \
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"movl %5,%%esp\n\t" /* restore ESP */ \
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"movl $1f,%1\n\t" /* save EIP */ \
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"pushl %6\n\t" /* restore EIP */ \
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"jmp __switch_to\n" \
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"1:\t" \
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"popl %%ebp\n\t" \
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"popfl" \
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:"=m" (prev->thread.esp),"=m" (prev->thread.eip), \
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"=a" (last),"=S" (esi),"=D" (edi) \
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:"m" (next->thread.esp),"m" (next->thread.eip), \
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"2" (prev), "d" (next)); \
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} while (0)
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#define _set_base(addr,base) do { unsigned long __pr; \
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__asm__ __volatile__ ("movw %%dx,%1\n\t" \
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"rorl $16,%%edx\n\t" \
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"movb %%dl,%2\n\t" \
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"movb %%dh,%3" \
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:"=&d" (__pr) \
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:"m" (*((addr)+2)), \
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"m" (*((addr)+4)), \
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"m" (*((addr)+7)), \
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"0" (base) \
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); } while(0)
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#define _set_limit(addr,limit) do { unsigned long __lr; \
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__asm__ __volatile__ ("movw %%dx,%1\n\t" \
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"rorl $16,%%edx\n\t" \
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"movb %2,%%dh\n\t" \
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"andb $0xf0,%%dh\n\t" \
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"orb %%dh,%%dl\n\t" \
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"movb %%dl,%2" \
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:"=&d" (__lr) \
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:"m" (*(addr)), \
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"m" (*((addr)+6)), \
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"0" (limit) \
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); } while(0)
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#define set_base(ldt,base) _set_base( ((char *)&(ldt)) , (base) )
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#define set_limit(ldt,limit) _set_limit( ((char *)&(ldt)) , ((limit)-1) )
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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*/
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#define loadsegment(seg,value) \
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asm volatile("\n" \
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"1:\t" \
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"mov %0,%%" #seg "\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3:\t" \
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"pushl $0\n\t" \
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"popl %%" #seg "\n\t" \
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"jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n\t" \
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".align 4\n\t" \
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".long 1b,3b\n" \
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".previous" \
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: :"rm" (value))
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/*
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* Save a segment register away
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*/
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#define savesegment(seg, value) \
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asm volatile("mov %%" #seg ",%0":"=rm" (value))
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static inline void native_clts(void)
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{
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asm volatile ("clts");
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}
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr0(unsigned long val)
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{
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asm volatile("movl %0,%%cr0": :"r" (val));
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}
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static inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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{
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asm volatile("movl %0,%%cr2": :"r" (val));
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}
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static inline unsigned long native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("movl %0,%%cr3": :"r" (val));
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
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return val;
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}
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static inline unsigned long native_read_cr4_safe(void)
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{
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unsigned long val;
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/* This could fault if %cr4 does not exist */
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asm("1: movl %%cr4, %0 \n"
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"2: \n"
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".section __ex_table,\"a\" \n"
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".long 1b,2b \n"
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".previous \n"
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: "=r" (val): "0" (0));
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return val;
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}
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static inline void native_write_cr4(unsigned long val)
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{
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asm volatile("movl %0,%%cr4": :"r" (val));
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}
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define read_cr0() (native_read_cr0())
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#define write_cr0(x) (native_write_cr0(x))
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#define read_cr2() (native_read_cr2())
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#define write_cr2(x) (native_write_cr2(x))
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#define read_cr3() (native_read_cr3())
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#define write_cr3(x) (native_write_cr3(x))
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#define read_cr4() (native_read_cr4())
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#define read_cr4_safe() (native_read_cr4_safe())
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#define write_cr4(x) (native_write_cr4(x))
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#define wbinvd() (native_wbinvd())
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/* Clear the 'TS' bit */
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#define clts() (native_clts())
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#endif/* CONFIG_PARAVIRT */
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/* Set the 'TS' bit */
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#define stts() write_cr0(8 | read_cr0())
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#endif /* __KERNEL__ */
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static inline unsigned long get_limit(unsigned long segment)
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{
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unsigned long __limit;
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__asm__("lsll %1,%0"
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:"=r" (__limit):"r" (segment));
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return __limit+1;
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}
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#define nop() __asm__ __volatile__ ("nop")
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#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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#ifdef CONFIG_X86_CMPXCHG64
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/*
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* The semantics of XCHGCMP8B are a bit strange, this is why
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* there is a loop and the loading of %%eax and %%edx has to
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* be inside. This inlines well in most cases, the cached
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* cost is around ~38 cycles. (in the future we might want
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* to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
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* might have an implicit FPU-save as a cost, so it's not
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* clear which path to go.)
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*
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* cmpxchg8b must be used with the lock prefix here to allow
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* the instruction to be executed atomically, see page 3-102
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* of the instruction set reference 24319102.pdf. We need
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* the reader side to see the coherent 64bit value.
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*/
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static inline void __set_64bit (unsigned long long * ptr,
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unsigned int low, unsigned int high)
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{
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__asm__ __volatile__ (
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"\n1:\t"
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"movl (%0), %%eax\n\t"
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"movl 4(%0), %%edx\n\t"
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"lock cmpxchg8b (%0)\n\t"
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"jnz 1b"
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: /* no outputs */
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: "D"(ptr),
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"b"(low),
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"c"(high)
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: "ax","dx","memory");
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}
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static inline void __set_64bit_constant (unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
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}
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#define ll_low(x) *(((unsigned int*)&(x))+0)
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#define ll_high(x) *(((unsigned int*)&(x))+1)
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static inline void __set_64bit_var (unsigned long long *ptr,
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unsigned long long value)
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{
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__set_64bit(ptr,ll_low(value), ll_high(value));
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}
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#define set_64bit(ptr,value) \
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(__builtin_constant_p(value) ? \
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__set_64bit_constant(ptr, value) : \
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__set_64bit_var(ptr, value) )
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#define _set_64bit(ptr,value) \
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(__builtin_constant_p(value) ? \
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__set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
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__set_64bit(ptr, ll_low(value), ll_high(value)) )
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#endif
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/*
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument. --ANK
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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:"=q" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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:"=r" (x)
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:"m" (*__xg(ptr)), "0" (x)
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:"memory");
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break;
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}
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return x;
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}
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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#ifdef CONFIG_X86_CMPXCHG
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#define __HAVE_ARCH_CMPXCHG 1
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#define sync_cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#endif
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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/*
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* Always use locked operations when touching memory shared with a
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* hypervisor, since the system may be SMP even if the guest kernel
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* isn't.
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*/
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static inline unsigned long __sync_cmpxchg(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__("lock; cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__("lock; cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__("lock; cmpxchgl %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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#ifndef CONFIG_X86_CMPXCHG
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/*
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* Building a kernel capable running on 80386. It may be necessary to
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* simulate the cmpxchg on the 80386 CPU. For that purpose we define
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* a function for each of the sizes we support.
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*/
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extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
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extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
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extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
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static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 1:
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return cmpxchg_386_u8(ptr, old, new);
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case 2:
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return cmpxchg_386_u16(ptr, old, new);
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case 4:
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return cmpxchg_386_u32(ptr, old, new);
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}
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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if (likely(boot_cpu_data.x86 > 3)) \
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__ret = __cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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else \
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__ret = cmpxchg_386((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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__ret; \
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})
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#endif
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#ifdef CONFIG_X86_CMPXCHG64
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static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
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unsigned long long new)
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{
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unsigned long long prev;
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__asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
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: "=A"(prev)
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: "b"((unsigned long)new),
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"c"((unsigned long)(new >> 32)),
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"m"(*__xg(ptr)),
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"0"(old)
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: "memory");
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return prev;
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}
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#define cmpxchg64(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
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(unsigned long long)(n)))
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#endif
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*
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* For now, "wmb()" doesn't actually do anything, as all
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* Intel CPU's follow what Intel calls a *Processor Order*,
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* in which all writes are seen in the program order even
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* outside the CPU.
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*
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* I expect future Intel CPU's to have a weaker ordering,
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* but I'd also expect them to finally get their act together
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* and add some real memory barriers if so.
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*
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* Some non intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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/*
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* Actually only lfence would be needed for mb() because all stores done
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* by the kernel should be already ordered. But keep a full barrier for now.
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*/
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#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
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#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
|
|
* x = a;
|
|
* </programlisting>
|
|
*
|
|
* does not enforce ordering, since there is no data dependency between
|
|
* the read of "a" and the read of "b". Therefore, on some CPUs, such
|
|
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
|
|
* in cases like this where there are no data dependencies.
|
|
**/
|
|
|
|
#define read_barrier_depends() do { } while(0)
|
|
|
|
#ifdef CONFIG_X86_OOSTORE
|
|
/* Actually there are no OOO store capable CPUs for now that do SSE,
|
|
but make it already an possibility. */
|
|
#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
|
|
#else
|
|
#define wmb() __asm__ __volatile__ ("": : :"memory")
|
|
#endif
|
|
|
|
#ifdef CONFIG_SMP
|
|
#define smp_mb() mb()
|
|
#define smp_rmb() rmb()
|
|
#define smp_wmb() wmb()
|
|
#define smp_read_barrier_depends() read_barrier_depends()
|
|
#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
|
|
#else
|
|
#define smp_mb() barrier()
|
|
#define smp_rmb() barrier()
|
|
#define smp_wmb() barrier()
|
|
#define smp_read_barrier_depends() do { } while(0)
|
|
#define set_mb(var, value) do { var = value; barrier(); } while (0)
|
|
#endif
|
|
|
|
#include <linux/irqflags.h>
|
|
|
|
/*
|
|
* disable hlt during certain critical i/o operations
|
|
*/
|
|
#define HAVE_DISABLE_HLT
|
|
void disable_hlt(void);
|
|
void enable_hlt(void);
|
|
|
|
extern int es7000_plat;
|
|
void cpu_idle_wait(void);
|
|
|
|
/*
|
|
* On SMP systems, when the scheduler does migration-cost autodetection,
|
|
* it needs a way to flush as much of the CPU's caches as possible:
|
|
*/
|
|
static inline void sched_cacheflush(void)
|
|
{
|
|
wbinvd();
|
|
}
|
|
|
|
extern unsigned long arch_align_stack(unsigned long sp);
|
|
extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
|
|
|
|
void default_idle(void);
|
|
|
|
#endif
|