041cadca70
This is the basic devicetree support for C6X. Currently, four boards are supported. Each one uses a different SoC part. Two of the four supported SoCs are multicore. One with 3 cores and the other with 6 cores. There is no coherency between the core-level caches, so SMP is not an option. It is possible to run separate kernel instances on the various cores. There is currently no C6X bootloader support for device trees so we build in the DTB for now. There are some interesting twists to the hardware which are of note for device tree support. Each core has its own interrupt controller which is controlled by special purpose core registers. This core controller provides 12 general purpose prioritized interrupt sources. Each core is contained within a hardware "module" which provides L1 and L2 caches, power control, and another interrupt controller which cascades into the core interrupt controller. These core module functions are controlled by memory mapped registers. The addresses for these registers are the same for each core. That is, when coreN accesses a module-level MMIO register at a given address, it accesses the register for coreN even though other cores would use the same address to access the register in the module containing those cores. Other hardware modules (timers, enet, etc) which are memory mapped can be accessed by all cores. The timers need some further explanation for multicore SoCs. Even though all timer control registers are visible to all cores, interrupt routing or other considerations may make a given timer more suitable for use by a core than some other timer. Because of this and the desire to have the same image run on more than one core, the timer nodes have a "ti,core-mask" property which is used by the driver to scan for a suitable timer to use. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
90 lines
1.7 KiB
Plaintext
90 lines
1.7 KiB
Plaintext
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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reg = <0>;
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model = "ti,c64x+";
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};
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cpu@1 {
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device_type = "cpu";
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reg = <1>;
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model = "ti,c64x+";
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};
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cpu@2 {
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device_type = "cpu";
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reg = <2>;
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model = "ti,c64x+";
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};
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};
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soc {
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compatible = "simple-bus";
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model = "tms320c6474";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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core_pic: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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compatible = "ti,c64x+core-pic";
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};
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megamod_pic: interrupt-controller@1800000 {
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compatible = "ti,c64x+megamod-pic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1800000 0x1000>;
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interrupt-parent = <&core_pic>;
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};
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cache-controller@1840000 {
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compatible = "ti,c64x+cache";
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reg = <0x01840000 0x8400>;
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};
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timer3: timer@2940000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x04 >;
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reg = <0x2940000 0x40>;
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};
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timer4: timer@2950000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x02 >;
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reg = <0x2950000 0x40>;
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};
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timer5: timer@2960000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x2960000 0x40>;
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};
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device-state-controller@2880800 {
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compatible = "ti,c64x+dscr";
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reg = <0x02880800 0x400>;
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ti,dscr-devstat = <0x004>;
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ti,dscr-silicon-rev = <0x014 28 0xf>;
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ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
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0x38 0 0 1 2>;
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};
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clock-controller@29a0000 {
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compatible = "ti,c6474-pll", "ti,c64x+pll";
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reg = <0x029a0000 0x200>;
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ti,c64x+pll-bypass-delay = <120>;
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ti,c64x+pll-reset-delay = <30000>;
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ti,c64x+pll-lock-delay = <60000>;
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};
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};
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};
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