a701fe3851
The ISP clock registers belong to the ISP power domain and may change
their values if this power domain is switched off/on. Add
CLK_GET_RATE_NOCACHE flags to ensure we do not rely on invalid cached
data when setting or getting frequency of those clocks.
Without this fix the FIMC-IS Cortex-A5 core and AXI bus clocks have
incorrect frequencies, which breaks the ISP operation and starting the
video pipeline fails with timeouts reported by the FIMC-IS firmware.
See related commit
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| .. | ||
| Makefile | ||
| clk-exynos-audss.c | ||
| clk-exynos4.c | ||
| clk-exynos5250.c | ||
| clk-exynos5420.c | ||
| clk-exynos5440.c | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk.c | ||
| clk.h | ||