8deab1144b
This is an update to the earlier patch for the sibyte headers, and superceeds the previous patch. Changes were necessary to get the tbprof driver working on the bcm1480. Patch to update Sibyte header files to match master versions maintained at Broadcom. This patch also corrects some whitespace problems, and (hopefully) shouldn't introduce any new ones. Signed-off-by: Mark Mason <mason@broadcom.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
551 lines
23 KiB
C
551 lines
23 KiB
C
/* *********************************************************************
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* SB1250 Board Support Package
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*
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* Memory Controller constants File: sb1250_mc.h
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*
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* This module contains constants and macros useful for
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* programming the memory controller.
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*
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* SB1250 specification level: User's manual 1/02/02
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*
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*********************************************************************
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*
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* Copyright 2000,2001,2002,2003
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* Broadcom Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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********************************************************************* */
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#ifndef _SB1250_MC_H
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#define _SB1250_MC_H
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#include "sb1250_defs.h"
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/*
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* Memory Channel Config Register (table 6-14)
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*/
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#define S_MC_RESERVED0 0
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#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0)
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#define S_MC_CHANNEL_SEL 8
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#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL)
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#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL)
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#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL)
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#define S_MC_BANK0_MAP 16
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#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP)
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#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP)
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#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP)
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#define K_MC_BANK0_MAP_DEFAULT 0x00
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#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
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#define S_MC_BANK1_MAP 20
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#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP)
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#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP)
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#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP)
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#define K_MC_BANK1_MAP_DEFAULT 0x08
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#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
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#define S_MC_BANK2_MAP 24
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#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP)
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#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP)
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#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP)
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#define K_MC_BANK2_MAP_DEFAULT 0x09
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#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
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#define S_MC_BANK3_MAP 28
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#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP)
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#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP)
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#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP)
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#define K_MC_BANK3_MAP_DEFAULT 0x0C
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#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
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#define M_MC_RESERVED1 _SB_MAKEMASK(8,32)
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#define S_MC_QUEUE_SIZE 40
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#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE)
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#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE)
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#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE)
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#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
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#define S_MC_AGE_LIMIT 44
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#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT)
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#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT)
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#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT)
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#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
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#define S_MC_WR_LIMIT 48
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#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT)
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#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT)
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#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT)
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#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
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#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
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#define M_MC_RESERVED2 _SB_MAKEMASK(3,53)
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#define S_MC_CS_MODE 56
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#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE)
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#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE)
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#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE)
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#define K_MC_CS_MODE_MSB_CS 0
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#define K_MC_CS_MODE_INTLV_CS 15
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#define K_MC_CS_MODE_MIXED_CS_10 12
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#define K_MC_CS_MODE_MIXED_CS_30 6
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#define K_MC_CS_MODE_MIXED_CS_32 3
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#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
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#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
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#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
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#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
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#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
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#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
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#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
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#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
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#define M_MC_DEBUG _SB_MAKEMASK1(63)
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#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
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V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
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V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
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M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
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/*
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* Memory clock config register (Table 6-15)
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*
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* Note: this field has been updated to be consistent with the errata to 0.2
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*/
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#define S_MC_CLK_RATIO 0
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#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO)
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#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO)
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#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO)
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#define K_MC_CLK_RATIO_2X 4
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#define K_MC_CLK_RATIO_25X 5
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#define K_MC_CLK_RATIO_3X 6
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#define K_MC_CLK_RATIO_35X 7
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#define K_MC_CLK_RATIO_4X 8
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#define K_MC_CLK_RATIO_45X 9
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#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
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#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
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#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
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#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
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#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
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#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
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#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
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#define S_MC_REF_RATE 8
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#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE)
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#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE)
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#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE)
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#define K_MC_REF_RATE_100MHz 0x62
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#define K_MC_REF_RATE_133MHz 0x81
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#define K_MC_REF_RATE_200MHz 0xC4
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#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
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#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
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#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
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#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
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#define S_MC_CLOCK_DRIVE 16
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#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE)
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#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE)
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#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE)
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#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
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#define S_MC_DATA_DRIVE 20
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#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE)
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#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE)
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#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE)
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#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
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#define S_MC_ADDR_DRIVE 24
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#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE)
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#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE)
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#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)
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#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
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#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
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#endif /* 1250 PASS3 || 112x PASS1 */
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#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
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#define S_MC_DQI_SKEW 32
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#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW)
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#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW)
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#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW)
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#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
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#define S_MC_DQO_SKEW 40
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#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW)
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#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW)
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#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW)
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#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
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#define S_MC_ADDR_SKEW 48
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#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW)
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#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW)
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#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW)
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#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
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#define S_MC_DLL_DEFAULT 56
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#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT)
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#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT)
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#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT)
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#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
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#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
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V_MC_ADDR_SKEW_DEFAULT | \
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V_MC_DQO_SKEW_DEFAULT | \
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V_MC_DQI_SKEW_DEFAULT | \
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V_MC_ADDR_DRIVE_DEFAULT | \
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V_MC_DATA_DRIVE_DEFAULT | \
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V_MC_CLOCK_DRIVE_DEFAULT | \
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V_MC_REF_RATE_DEFAULT
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/*
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* DRAM Command Register (Table 6-13)
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*/
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#define S_MC_COMMAND 0
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#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND)
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#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND)
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#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND)
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#define K_MC_COMMAND_EMRS 0
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#define K_MC_COMMAND_MRS 1
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#define K_MC_COMMAND_PRE 2
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#define K_MC_COMMAND_AR 3
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#define K_MC_COMMAND_SETRFSH 4
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#define K_MC_COMMAND_CLRRFSH 5
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#define K_MC_COMMAND_SETPWRDN 6
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#define K_MC_COMMAND_CLRPWRDN 7
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#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS)
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#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS)
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#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE)
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#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR)
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#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
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#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
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#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
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#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
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#define M_MC_CS0 _SB_MAKEMASK1(4)
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#define M_MC_CS1 _SB_MAKEMASK1(5)
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#define M_MC_CS2 _SB_MAKEMASK1(6)
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#define M_MC_CS3 _SB_MAKEMASK1(7)
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/*
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* DRAM Mode Register (Table 6-14)
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*/
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#define S_MC_EMODE 0
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#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE)
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#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE)
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#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE)
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#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
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#define S_MC_MODE 16
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#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE)
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#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE)
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#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE)
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#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
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#define S_MC_DRAM_TYPE 32
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#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE)
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#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE)
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#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE)
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#define K_MC_DRAM_TYPE_JEDEC 0
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#define K_MC_DRAM_TYPE_FCRAM 1
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#define K_MC_DRAM_TYPE_SGRAM 2
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#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
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#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
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#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
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#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
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#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
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#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
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#endif /* 1250 PASS3 || 112x PASS1 */
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/*
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* SDRAM Timing Register (Table 6-15)
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*/
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#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60)
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#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61)
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#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
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#define S_MC_tFIFO 56
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#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO)
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#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO)
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#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO)
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#define K_MC_tFIFO_DEFAULT 1
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#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
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#define S_MC_tRFC 52
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#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC)
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#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC)
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#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC)
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#define K_MC_tRFC_DEFAULT 12
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#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
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#if SIBYTE_HDR_FEATURE(1250, PASS3)
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#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */
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#endif
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#define S_MC_tCwCr 40
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#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr)
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#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr)
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#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr)
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#define K_MC_tCwCr_DEFAULT 4
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#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
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#define S_MC_tRCr 28
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#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr)
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#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr)
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#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr)
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#define K_MC_tRCr_DEFAULT 9
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#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
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#define S_MC_tRCw 24
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#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw)
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#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw)
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#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw)
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#define K_MC_tRCw_DEFAULT 10
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#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
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#define S_MC_tRRD 20
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#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD)
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#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD)
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#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD)
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#define K_MC_tRRD_DEFAULT 2
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#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
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#define S_MC_tRP 16
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#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP)
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#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP)
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#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP)
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#define K_MC_tRP_DEFAULT 4
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#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
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#define S_MC_tCwD 8
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#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD)
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#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD)
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#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD)
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#define K_MC_tCwD_DEFAULT 1
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#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
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#define M_tCrDh _SB_MAKEMASK1(7)
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#define M_MC_tCrDh M_tCrDh
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#define S_MC_tCrD 4
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#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD)
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#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD)
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#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD)
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#define K_MC_tCrD_DEFAULT 2
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#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
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#define S_MC_tRCD 0
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#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD)
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#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD)
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#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD)
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#define K_MC_tRCD_DEFAULT 3
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#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
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#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
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V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
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V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
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V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
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V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
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V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
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V_MC_tRP(K_MC_tRP_DEFAULT) | \
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V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
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V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
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V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
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M_MC_r2rIDLE_TWOCYCLES
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/*
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* Errata says these are not the default
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* M_MC_w2rIDLE_TWOCYCLES | \
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* M_MC_r2wIDLE_TWOCYCLES | \
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*/
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/*
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* Chip Select Start Address Register (Table 6-17)
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*/
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#define S_MC_CS0_START 0
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#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START)
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#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START)
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#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START)
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#define S_MC_CS1_START 16
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#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START)
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#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START)
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#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START)
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#define S_MC_CS2_START 32
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#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START)
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#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START)
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#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START)
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#define S_MC_CS3_START 48
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#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START)
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#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START)
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#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START)
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/*
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* Chip Select End Address Register (Table 6-18)
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*/
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#define S_MC_CS0_END 0
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#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END)
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#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END)
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#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END)
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#define S_MC_CS1_END 16
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#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END)
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#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END)
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#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END)
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#define S_MC_CS2_END 32
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#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END)
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#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END)
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#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END)
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#define S_MC_CS3_END 48
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#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END)
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#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END)
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#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END)
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/*
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* Chip Select Interleave Register (Table 6-19)
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*/
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#define S_MC_INTLV_RESERVED 0
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#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED)
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#define S_MC_INTERLEAVE 7
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#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE)
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#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE)
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#define S_MC_INTLV_MBZ 25
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#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ)
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/*
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* Row Address Bits Register (Table 6-20)
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*/
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#define S_MC_RAS_RESERVED 0
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#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED)
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#define S_MC_RAS_SELECT 12
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#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT)
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#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT)
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#define S_MC_RAS_MBZ 37
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#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ)
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/*
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* Column Address Bits Register (Table 6-21)
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*/
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#define S_MC_CAS_RESERVED 0
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#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED)
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#define S_MC_CAS_SELECT 5
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#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT)
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#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT)
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#define S_MC_CAS_MBZ 23
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#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ)
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/*
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* Bank Address Address Bits Register (Table 6-22)
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*/
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#define S_MC_BA_RESERVED 0
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#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED)
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#define S_MC_BA_SELECT 5
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#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT)
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#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT)
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#define S_MC_BA_MBZ 25
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#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ)
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/*
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* Chip Select Attribute Register (Table 6-23)
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*/
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#define K_MC_CS_ATTR_CLOSED 0
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#define K_MC_CS_ATTR_CASCHECK 1
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#define K_MC_CS_ATTR_HINT 2
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#define K_MC_CS_ATTR_OPEN 3
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#define S_MC_CS0_PAGE 0
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#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE)
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#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE)
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#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE)
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#define S_MC_CS1_PAGE 16
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#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE)
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#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE)
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#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE)
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#define S_MC_CS2_PAGE 32
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#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE)
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#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE)
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#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE)
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#define S_MC_CS3_PAGE 48
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#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE)
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#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE)
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#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE)
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/*
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* ECC Test ECC Register (Table 6-25)
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*/
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#define S_MC_ECC_INVERT 0
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#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT)
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#endif
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