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linux/arch/mips/include/asm/mach-cavium-octeon
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Chandrakala Chavva 7716e6548a Octeon: Fix interrupt irq settings for performance counters. 
Octeon uses different interrupt irq for timer and performance counters.
Set CvmCtl[IPPCI] to correct irq value very early.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/2085/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 		2011-05-19 09:55:49 +01:00
..
cpu-feature-overrides.h MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II. 2010-10-29 19:08:38 +01:00
dma-coherence.h MIPS: Octeon: Rewrite DMA mapping functions. 2010-10-29 19:08:32 +01:00
irq.h MIPS: Octeon: Rewrite interrupt handling code. 2011-03-29 14:48:06 +02:00
kernel-entry-init.h Octeon: Fix interrupt irq settings for performance counters. 2011-05-19 09:55:49 +01:00
war.h
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