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Illia Ragozin cd272d1ea7 ARM: 7696/1: Fix kexec by setting outer_cache.inv_all for Feroceon 
On Feroceon the L2 cache becomes non-coherent with the CPU
when the L1 caches are disabled. Thus the L2 needs to be invalidated
after both L1 caches are disabled.

On kexec before the starting the code for relocation the kernel,
the L1 caches are disabled in cpu_froc_fin (cpu_v7_proc_fin for Feroceon),
but after L2 cache is never invalidated, because inv_all is not set
in cache-feroceon-l2.c.
So kernel relocation and decompression may has (and usually has) errors.
Setting the function enables L2 invalidation and fixes the issue.

Cc: <stable@vger.kernel.org>
Signed-off-by: Illia Ragozin <illia.ragozin@grapecom.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
 		2013-04-17 16:53:27 +01:00
..
Kconfig ARM: cache: remove ARMv3 support code 2013-03-26 09:55:23 +00:00
Makefile ARM: cache: remove ARMv3 support code 2013-03-26 09:55:23 +00:00
abort-ev4.S
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abort-ev4t.S
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abort-ev5t.S
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abort-ev5tj.S
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abort-ev6.S
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abort-ev7.S
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abort-lv4t.S
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abort-macro.S
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abort-nommu.S
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alignment.c ARM: fix scheduling while atomic warning in alignment handling code 2013-02-25 16:10:42 +00:00
cache-aurora-l2.h ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl 2012-11-06 19:47:35 +00:00
cache-fa.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
cache-feroceon-l2.c ARM: 7696/1: Fix kexec by setting outer_cache.inv_all for Feroceon 2013-04-17 16:53:27 +01:00
cache-l2x0.c ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init 2013-04-03 16:45:48 +01:00
cache-tauros2.c
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cache-v4.S ARM: mm: remove broken condition check for v4 flushing 2013-03-26 09:55:34 +00:00
cache-v4wb.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
cache-v4wt.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
cache-v6.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
cache-v7.S arm: Add v7_invalidate_l1 to cache-v7.S 2013-02-11 19:37:24 -08:00
cache-xsc3l2.c
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context.c ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations) 2013-04-03 16:45:49 +01:00
copypage-fa.c
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copypage-feroceon.c
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copypage-v4mc.c
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copypage-v4wb.c
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copypage-v4wt.c
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copypage-v6.c
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copypage-xsc3.c
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copypage-xscale.c
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dma-mapping.c ARM: DMA-mapping: add missing GFP_DMA flag for atomic buffer allocation 2013-03-14 09:25:19 +01:00
extable.c
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fault-armv.c mm: replace vma prio_tree with an interval tree 2012-10-09 16:22:39 +09:00
fault.c readahead: fault retry breaks mmap file read random detection 2012-10-09 16:22:47 +09:00
fault.h
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flush.c mm: replace vma prio_tree with an interval tree 2012-10-09 16:22:39 +09:00
fsr-2level.c
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fsr-3level.c
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highmem.c
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idmap.c ARM: 7661/1: mm: perform explicit branch predictor maintenance when required 2013-03-03 22:54:16 +00:00
init.c
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iomap.c
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ioremap.c ARM: 7646/1: mm: use static_vm for managing static mapped areas 2013-02-16 17:54:22 +00:00
mm.h ARM: 7645/1: ioremap: introduce an infrastructure for static mapped area 2013-02-16 17:54:22 +00:00
mmap.c Merge branch 'akpm' (Andrew's patchbomb) 2012-12-11 18:05:37 -08:00
mmu.c ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch() 2013-04-17 16:53:24 +01:00
nommu.c
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pabort-legacy.S
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pabort-v6.S
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pabort-v7.S
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pgd.c
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proc-arm7tdmi.S
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proc-arm9tdmi.S
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proc-arm720.S
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proc-arm740.S ARM: mm: fix numerous hideous errors in proc-arm740.S 2013-03-26 09:55:33 +00:00
proc-arm920.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
proc-arm922.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm925.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm926.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
proc-arm940.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm946.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm1020.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm1020e.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm1022.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-arm1026.S ARM: mm: implement LoUIS API for cache maintenance ops 2012-09-25 11:20:25 +01:00
proc-fa526.S
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proc-feroceon.S ARM: 7542/1: mm: fix cache LoUIS API for xscale and feroceon 2012-09-28 21:09:50 +01:00
proc-macros.S ARM: 7649/1: mm: mm->context.id fix for big-endian 2013-02-16 17:54:26 +00:00
proc-mohawk.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
proc-sa110.S
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proc-sa1100.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
proc-syms.c ARM: modules: don't export cpu_set_pte_ext when !MMU 2013-03-26 09:55:34 +00:00
proc-v6.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
proc-v7-2level.S ARM: 7650/1: mm: replace direct access to mm->context.id with new macro 2013-02-16 17:54:27 +00:00
proc-v7-3level.S ARM: 7652/1: mm: fix missing use of 'asid' to get asid value from mm->context.id 2013-03-03 22:54:12 +00:00
proc-v7.S ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs 2013-03-22 17:16:56 +00:00
proc-xsc3.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
proc-xscale.S ARM: Do 15e0d9e37c (ARM: pm: let platforms select cpu_suspend support) properly 2013-04-08 12:00:38 +01:00
tcm.h ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch() 2013-04-17 16:53:24 +01:00
tlb-fa.S
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tlb-v4.S
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tlb-v4wb.S
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tlb-v4wbi.S
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tlb-v6.S
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tlb-v7.S
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