linux/Documentation/arm64
Catalin Marinas ce8c80c536 arm64: Add workaround for Cortex-A76 erratum 1286807
On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual address
for a cacheable mapping of a location is being accessed by a core while
another core is remapping the virtual address to a new physical page
using the recommended break-before-make sequence, then under very rare
circumstances TLBI+DSB completes before a read using the translation
being invalidated has been observed by other observers. The workaround
repeats the TLBI+DSB operation and is shared with the Qualcomm Falkor
erratum 1009

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-11-29 16:45:45 +00:00
..
acpi_object_usage.txt ARM64: ACPI: Update documentation for latest specification version 2016-06-21 16:26:09 +01:00
arm-acpi.txt ARM64: ACPI: Update documentation for latest specification version 2016-06-21 16:26:09 +01:00
booting.txt arm64: add the initrd region to the linear mapping explicitly 2016-04-14 16:20:45 +01:00
cpu-feature-registers.txt arm64: Expose Arm v8.4 features 2018-03-19 18:14:27 +00:00
elf_hwcaps.txt arm64: docs: Document SSBS HWCAP 2018-10-01 16:28:17 +01:00
hugetlbpage.txt Documentation/arm64: HugeTLB page implementation 2018-10-10 18:08:36 +01:00
legacy_instructions.txt arm64: Emulate SETEND for AArch32 tasks 2015-01-23 17:11:44 +00:00
memory.txt arm64: KVM: Allow mapping of vectors outside of the RAM region 2018-03-19 13:06:46 +00:00
silicon-errata.txt arm64: Add workaround for Cortex-A76 erratum 1286807 2018-11-29 16:45:45 +00:00
sve.txt Documentation/arm64/sve: Couple of improvements and typos 2018-08-29 11:33:19 +01:00
tagged-pointers.txt arm64: documentation: document tagged pointer stack constraints 2017-05-09 17:43:18 +01:00