85 lines
2.0 KiB
C
85 lines
2.0 KiB
C
/*
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* SH-ARM CPU-specific DMA definitions, used by both DMA drivers
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*
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* Copyright (C) 2012 Renesas Solutions Corp
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*
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* Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DMA_REGISTER_H
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#define DMA_REGISTER_H
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/*
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* Direct Memory Access Controller
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*/
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/* Transmit sizes and respective CHCR register values */
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enum {
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XMIT_SZ_8BIT = 0,
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XMIT_SZ_16BIT = 1,
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XMIT_SZ_32BIT = 2,
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XMIT_SZ_64BIT = 7,
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XMIT_SZ_128BIT = 3,
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XMIT_SZ_256BIT = 4,
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XMIT_SZ_512BIT = 5,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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static const unsigned int dma_ts_shift[] = {
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[XMIT_SZ_8BIT] = 0,
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[XMIT_SZ_16BIT] = 1,
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[XMIT_SZ_32BIT] = 2,
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[XMIT_SZ_64BIT] = 3,
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[XMIT_SZ_128BIT] = 4,
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[XMIT_SZ_256BIT] = 5,
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[XMIT_SZ_512BIT] = 6,
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};
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#define TS_LOW_BIT 0x3 /* --xx */
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#define TS_HI_BIT 0xc /* xx-- */
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#define TS_LOW_SHIFT (3)
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#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
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#define TS_INDEX2VAL(i) \
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((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
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(((i) & TS_HI_BIT) << TS_HI_SHIFT))
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#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
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#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
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/*
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* USB High-Speed DMAC
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*/
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/* Transmit sizes and respective CHCR register values */
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enum {
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USBTS_XMIT_SZ_8BYTE = 0,
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USBTS_XMIT_SZ_16BYTE = 1,
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USBTS_XMIT_SZ_32BYTE = 2,
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};
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/* log2(size / 8) - used to calculate number of transfers */
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static const unsigned int dma_usbts_shift[] = {
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[USBTS_XMIT_SZ_8BYTE] = 3,
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[USBTS_XMIT_SZ_16BYTE] = 4,
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[USBTS_XMIT_SZ_32BYTE] = 5,
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};
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#define USBTS_LOW_BIT 0x3 /* --xx */
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#define USBTS_HI_BIT 0x0 /* ---- */
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#define USBTS_LOW_SHIFT 6
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#define USBTS_HI_SHIFT 0
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#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
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#endif /* DMA_REGISTER_H */
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