Robert Richter d0e4120fda oprofile/x86: reserve counter msrs pairwise ... For AMD's and Intel's P6 generic performance counters have pairwise counter and control msrs. This patch changes the counter reservation in a way that both msrs must be registered. It joins some counter loops and also removes the unnecessary NUM_CONTROLS macro in the AMD implementation. Signed-off-by: Robert Richter <robert.richter@amd.com>		2010-05-04 11:35:26 +02:00
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backtrace.c	perf events, x86/stacktrace: Make stack walking optional	2009-12-17 09:56:19 +01:00
init.c	x86: coding style fixes to arch/x86/oprofile/init.c	2008-04-17 17:40:49 +02:00
Makefile	x86/oprofile: reanaming op_model_athlon.c to op_model_amd.c	2008-07-26 11:48:14 +02:00
nmi_int.c	oprofile/x86: rework error handler in nmi_setup()	2010-05-04 11:35:07 +02:00
nmi_timer_int.c	x86: coding style fixes to arch/x86/oprofile/nmi_timer_int.c	2008-04-17 17:40:50 +02:00
op_counter.h	oprofile: Implement performance counter multiplexing	2009-07-20 16:33:53 +02:00
op_model_amd.c	oprofile/x86: reserve counter msrs pairwise	2010-05-04 11:35:26 +02:00
op_model_p4.c	oprofile/x86: use kzalloc() instead of kmalloc()	2010-02-26 15:20:03 +01:00
op_model_ppro.c	oprofile/x86: reserve counter msrs pairwise	2010-05-04 11:35:26 +02:00
op_x86_model.h	oprofile/x86: add comment to counter-in-use warning	2010-02-26 15:14:34 +01:00