944 lines
22 KiB
C
944 lines
22 KiB
C
/*
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* arch/powerpc/platforms/pseries/xics.c
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*
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* Copyright 2000 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/threads.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/radix-tree.h>
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#include <linux/cpu.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/percpu.h>
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#include <asm/firmware.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/rtas.h>
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#include <asm/hvcall.h>
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#include <asm/machdep.h>
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#include "xics.h"
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#include "plpar_wrappers.h"
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static struct irq_host *xics_host;
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#define XICS_IPI 2
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#define XICS_IRQ_SPURIOUS 0
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/* Want a priority other than 0. Various HW issues require this. */
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#define DEFAULT_PRIORITY 5
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/*
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* Mark IPIs as higher priority so we can take them inside interrupts that
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* arent marked IRQF_DISABLED
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*/
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#define IPI_PRIORITY 4
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/* The least favored priority */
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#define LOWEST_PRIORITY 0xFF
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/* The number of priorities defined above */
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#define MAX_NUM_PRIORITIES 3
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static unsigned int default_server = 0xFF;
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static unsigned int default_distrib_server = 0;
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static unsigned int interrupt_server_size = 8;
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/* RTAS service tokens */
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static int ibm_get_xive;
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static int ibm_set_xive;
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static int ibm_int_on;
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static int ibm_int_off;
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struct xics_cppr {
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unsigned char stack[MAX_NUM_PRIORITIES];
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int index;
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};
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static DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
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/* Direct hardware low level accessors */
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/* The part of the interrupt presentation layer that we care about */
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struct xics_ipl {
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union {
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u32 word;
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u8 bytes[4];
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} xirr_poll;
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union {
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u32 word;
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u8 bytes[4];
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} xirr;
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u32 dummy;
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union {
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u32 word;
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u8 bytes[4];
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} qirr;
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};
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static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
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static inline unsigned int direct_xirr_info_get(void)
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{
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int cpu = smp_processor_id();
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return in_be32(&xics_per_cpu[cpu]->xirr.word);
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}
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static inline void direct_xirr_info_set(unsigned int value)
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{
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int cpu = smp_processor_id();
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out_be32(&xics_per_cpu[cpu]->xirr.word, value);
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}
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static inline void direct_cppr_info(u8 value)
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{
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int cpu = smp_processor_id();
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out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
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}
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static inline void direct_qirr_info(int n_cpu, u8 value)
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{
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out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
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}
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/* LPAR low level accessors */
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static inline unsigned int lpar_xirr_info_get(unsigned char cppr)
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{
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unsigned long lpar_rc;
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unsigned long return_value;
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lpar_rc = plpar_xirr(&return_value, cppr);
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if (lpar_rc != H_SUCCESS)
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panic(" bad return code xirr - rc = %lx\n", lpar_rc);
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return (unsigned int)return_value;
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}
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static inline void lpar_xirr_info_set(unsigned int value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_eoi(value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
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value);
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}
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static inline void lpar_cppr_info(u8 value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_cppr(value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code cppr - rc = %lx\n", lpar_rc);
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}
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static inline void lpar_qirr_info(int n_cpu , u8 value)
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{
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unsigned long lpar_rc;
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lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code qirr - rc = %lx\n", lpar_rc);
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}
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/* Interface to generic irq subsystem */
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#ifdef CONFIG_SMP
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/*
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* For the moment we only implement delivery to all cpus or one cpu.
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*
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* If the requested affinity is cpu_all_mask, we set global affinity.
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* If not we set it to the first cpu in the mask, even if multiple cpus
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* are set. This is so things like irqbalance (which set core and package
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* wide affinities) do the right thing.
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*/
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static int get_irq_server(unsigned int virq, const struct cpumask *cpumask,
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unsigned int strict_check)
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{
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if (!distribute_irqs)
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return default_server;
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if (!cpumask_equal(cpumask, cpu_all_mask)) {
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int server = cpumask_first_and(cpu_online_mask, cpumask);
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if (server < nr_cpu_ids)
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return get_hard_smp_processor_id(server);
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if (strict_check)
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return -1;
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}
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/*
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* Workaround issue with some versions of JS20 firmware that
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* deliver interrupts to cpus which haven't been started. This
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* happens when using the maxcpus= boot option.
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*/
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if (cpumask_equal(cpu_online_mask, cpu_present_mask))
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return default_distrib_server;
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return default_server;
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}
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#else
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#define get_irq_server(virq, cpumask, strict_check) (default_server)
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#endif
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static void xics_unmask_irq(unsigned int virq)
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{
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unsigned int irq;
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int call_status;
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int server;
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pr_devel("xics: unmask virq %d\n", virq);
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irq = (unsigned int)irq_map[virq].hwirq;
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pr_devel(" -> map to hwirq 0x%x\n", irq);
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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return;
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server = get_irq_server(virq, irq_to_desc(virq)->affinity, 0);
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
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DEFAULT_PRIORITY);
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if (call_status != 0) {
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printk(KERN_ERR
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"%s: ibm_set_xive irq %u server %x returned %d\n",
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__func__, irq, server, call_status);
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return;
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}
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/* Now unmask the interrupt (often a no-op) */
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call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
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if (call_status != 0) {
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printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n",
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__func__, irq, call_status);
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return;
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}
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}
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static unsigned int xics_startup(unsigned int virq)
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{
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/*
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* The generic MSI code returns with the interrupt disabled on the
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* card, using the MSI mask bits. Firmware doesn't appear to unmask
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* at that level, so we do it here by hand.
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*/
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if (irq_to_desc(virq)->msi_desc)
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unmask_msi_irq(virq);
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/* unmask it */
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xics_unmask_irq(virq);
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return 0;
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}
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static void xics_mask_real_irq(unsigned int irq)
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{
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int call_status;
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if (irq == XICS_IPI)
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return;
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call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
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if (call_status != 0) {
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printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n",
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__func__, irq, call_status);
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return;
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}
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/* Have to set XIVE to 0xff to be able to remove a slot */
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
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default_server, 0xff);
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if (call_status != 0) {
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printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n",
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__func__, irq, call_status);
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return;
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}
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}
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static void xics_mask_irq(unsigned int virq)
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{
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unsigned int irq;
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pr_devel("xics: mask virq %d\n", virq);
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irq = (unsigned int)irq_map[virq].hwirq;
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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return;
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xics_mask_real_irq(irq);
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}
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static void xics_mask_unknown_vec(unsigned int vec)
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{
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printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
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xics_mask_real_irq(vec);
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}
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static inline unsigned int xics_xirr_vector(unsigned int xirr)
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{
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/*
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* The top byte is the old cppr, to be restored on EOI.
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* The remaining 24 bits are the vector.
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*/
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return xirr & 0x00ffffff;
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}
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static void push_cppr(unsigned int vec)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
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return;
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if (vec == XICS_IPI)
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os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
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else
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os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
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}
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static unsigned int xics_get_irq_direct(void)
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{
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unsigned int xirr = direct_xirr_info_get();
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unsigned int vec = xics_xirr_vector(xirr);
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unsigned int irq;
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if (vec == XICS_IRQ_SPURIOUS)
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return NO_IRQ;
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irq = irq_radix_revmap_lookup(xics_host, vec);
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if (likely(irq != NO_IRQ)) {
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push_cppr(vec);
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return irq;
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}
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/* We don't have a linux mapping, so have rtas mask it. */
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xics_mask_unknown_vec(vec);
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/* We might learn about it later, so EOI it */
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direct_xirr_info_set(xirr);
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return NO_IRQ;
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}
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static unsigned int xics_get_irq_lpar(void)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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unsigned int xirr = lpar_xirr_info_get(os_cppr->stack[os_cppr->index]);
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unsigned int vec = xics_xirr_vector(xirr);
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unsigned int irq;
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if (vec == XICS_IRQ_SPURIOUS)
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return NO_IRQ;
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irq = irq_radix_revmap_lookup(xics_host, vec);
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if (likely(irq != NO_IRQ)) {
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push_cppr(vec);
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return irq;
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}
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/* We don't have a linux mapping, so have RTAS mask it. */
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xics_mask_unknown_vec(vec);
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/* We might learn about it later, so EOI it */
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lpar_xirr_info_set(xirr);
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return NO_IRQ;
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}
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static unsigned char pop_cppr(void)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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if (WARN_ON(os_cppr->index < 1))
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return LOWEST_PRIORITY;
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return os_cppr->stack[--os_cppr->index];
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}
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static void xics_eoi_direct(unsigned int virq)
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{
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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direct_xirr_info_set((pop_cppr() << 24) | irq);
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}
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static void xics_eoi_lpar(unsigned int virq)
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{
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unsigned int irq = (unsigned int)irq_map[virq].hwirq;
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iosync();
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lpar_xirr_info_set((pop_cppr() << 24) | irq);
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}
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static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
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{
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unsigned int irq;
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int status;
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int xics_status[2];
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int irq_server;
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irq = (unsigned int)irq_map[virq].hwirq;
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if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
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return -1;
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status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
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if (status) {
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printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
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__func__, irq, status);
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return -1;
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}
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irq_server = get_irq_server(virq, cpumask, 1);
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if (irq_server == -1) {
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char cpulist[128];
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cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
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printk(KERN_WARNING
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"%s: No online cpus in the mask %s for irq %d\n",
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__func__, cpulist, virq);
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return -1;
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}
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status = rtas_call(ibm_set_xive, 3, 1, NULL,
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irq, irq_server, xics_status[1]);
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if (status) {
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printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
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__func__, irq, status);
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return -1;
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}
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return 0;
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}
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static struct irq_chip xics_pic_direct = {
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.name = "XICS",
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.startup = xics_startup,
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.mask = xics_mask_irq,
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.unmask = xics_unmask_irq,
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.eoi = xics_eoi_direct,
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.set_affinity = xics_set_affinity
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};
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static struct irq_chip xics_pic_lpar = {
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.name = "XICS",
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.startup = xics_startup,
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.mask = xics_mask_irq,
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.unmask = xics_unmask_irq,
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.eoi = xics_eoi_lpar,
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.set_affinity = xics_set_affinity
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};
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/* Interface to arch irq controller subsystem layer */
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/* Points to the irq_chip we're actually using */
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static struct irq_chip *xics_irq_chip;
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static int xics_host_match(struct irq_host *h, struct device_node *node)
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{
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/* IBM machines have interrupt parents of various funky types for things
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* like vdevices, events, etc... The trick we use here is to match
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* everything here except the legacy 8259 which is compatible "chrp,iic"
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*/
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return !of_device_is_compatible(node, "chrp,iic");
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}
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static int xics_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
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/* Insert the interrupt mapping into the radix tree for fast lookup */
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irq_radix_revmap_insert(xics_host, virq, hw);
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irq_to_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
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return 0;
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}
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static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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/* Current xics implementation translates everything
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* to level. It is not technically right for MSIs but this
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* is irrelevant at this point. We might get smarter in the future
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*/
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*out_hwirq = intspec[0];
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*out_flags = IRQ_TYPE_LEVEL_LOW;
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return 0;
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}
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static struct irq_host_ops xics_host_ops = {
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.match = xics_host_match,
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.map = xics_host_map,
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.xlate = xics_host_xlate,
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};
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static void __init xics_init_host(void)
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{
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if (firmware_has_feature(FW_FEATURE_LPAR))
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xics_irq_chip = &xics_pic_lpar;
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else
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xics_irq_chip = &xics_pic_direct;
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xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
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XICS_IRQ_SPURIOUS);
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BUG_ON(xics_host == NULL);
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irq_set_default_host(xics_host);
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}
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/* Inter-processor interrupt support */
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#ifdef CONFIG_SMP
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/*
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* XICS only has a single IPI, so encode the messages per CPU
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*/
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static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
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static inline void smp_xics_do_message(int cpu, int msg)
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{
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|
unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
|
|
|
|
set_bit(msg, tgt);
|
|
mb();
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
lpar_qirr_info(cpu, IPI_PRIORITY);
|
|
else
|
|
direct_qirr_info(cpu, IPI_PRIORITY);
|
|
}
|
|
|
|
void smp_xics_message_pass(int target, int msg)
|
|
{
|
|
unsigned int i;
|
|
|
|
if (target < NR_CPUS) {
|
|
smp_xics_do_message(target, msg);
|
|
} else {
|
|
for_each_online_cpu(i) {
|
|
if (target == MSG_ALL_BUT_SELF
|
|
&& i == smp_processor_id())
|
|
continue;
|
|
smp_xics_do_message(i, msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
static irqreturn_t xics_ipi_dispatch(int cpu)
|
|
{
|
|
unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
|
|
|
|
WARN_ON(cpu_is_offline(cpu));
|
|
|
|
mb(); /* order mmio clearing qirr */
|
|
while (*tgt) {
|
|
if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
|
|
smp_message_recv(PPC_MSG_CALL_FUNCTION);
|
|
}
|
|
if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) {
|
|
smp_message_recv(PPC_MSG_RESCHEDULE);
|
|
}
|
|
if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) {
|
|
smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
|
|
}
|
|
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
|
|
if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) {
|
|
smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
|
|
}
|
|
#endif
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
direct_qirr_info(cpu, 0xff);
|
|
|
|
return xics_ipi_dispatch(cpu);
|
|
}
|
|
|
|
static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
lpar_qirr_info(cpu, 0xff);
|
|
|
|
return xics_ipi_dispatch(cpu);
|
|
}
|
|
|
|
static void xics_request_ipi(void)
|
|
{
|
|
unsigned int ipi;
|
|
int rc;
|
|
|
|
ipi = irq_create_mapping(xics_host, XICS_IPI);
|
|
BUG_ON(ipi == NO_IRQ);
|
|
|
|
/*
|
|
* IPIs are marked IRQF_DISABLED as they must run with irqs
|
|
* disabled
|
|
*/
|
|
set_irq_handler(ipi, handle_percpu_irq);
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
rc = request_irq(ipi, xics_ipi_action_lpar,
|
|
IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
|
|
else
|
|
rc = request_irq(ipi, xics_ipi_action_direct,
|
|
IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
|
|
BUG_ON(rc);
|
|
}
|
|
|
|
int __init smp_xics_probe(void)
|
|
{
|
|
xics_request_ipi();
|
|
|
|
return cpumask_weight(cpu_possible_mask);
|
|
}
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
/* Initialization */
|
|
|
|
static void xics_update_irq_servers(void)
|
|
{
|
|
int i, j;
|
|
struct device_node *np;
|
|
u32 ilen;
|
|
const u32 *ireg;
|
|
u32 hcpuid;
|
|
|
|
/* Find the server numbers for the boot cpu. */
|
|
np = of_get_cpu_node(boot_cpuid, NULL);
|
|
BUG_ON(!np);
|
|
|
|
ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
|
|
if (!ireg) {
|
|
of_node_put(np);
|
|
return;
|
|
}
|
|
|
|
i = ilen / sizeof(int);
|
|
hcpuid = get_hard_smp_processor_id(boot_cpuid);
|
|
|
|
/* Global interrupt distribution server is specified in the last
|
|
* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
|
|
* entry fom this property for current boot cpu id and use it as
|
|
* default distribution server
|
|
*/
|
|
for (j = 0; j < i; j += 2) {
|
|
if (ireg[j] == hcpuid) {
|
|
default_server = hcpuid;
|
|
default_distrib_server = ireg[j+1];
|
|
}
|
|
}
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
|
|
unsigned long size)
|
|
{
|
|
int i;
|
|
|
|
/* This may look gross but it's good enough for now, we don't quite
|
|
* have a hard -> linux processor id matching.
|
|
*/
|
|
for_each_possible_cpu(i) {
|
|
if (!cpu_present(i))
|
|
continue;
|
|
if (hw_id == get_hard_smp_processor_id(i)) {
|
|
xics_per_cpu[i] = ioremap(addr, size);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void __init xics_init_one_node(struct device_node *np,
|
|
unsigned int *indx)
|
|
{
|
|
unsigned int ilen;
|
|
const u32 *ireg;
|
|
|
|
/* This code does the theorically broken assumption that the interrupt
|
|
* server numbers are the same as the hard CPU numbers.
|
|
* This happens to be the case so far but we are playing with fire...
|
|
* should be fixed one of these days. -BenH.
|
|
*/
|
|
ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
|
|
|
|
/* Do that ever happen ? we'll know soon enough... but even good'old
|
|
* f80 does have that property ..
|
|
*/
|
|
WARN_ON(ireg == NULL);
|
|
if (ireg) {
|
|
/*
|
|
* set node starting index for this node
|
|
*/
|
|
*indx = *ireg;
|
|
}
|
|
ireg = of_get_property(np, "reg", &ilen);
|
|
if (!ireg)
|
|
panic("xics_init_IRQ: can't find interrupt reg property");
|
|
|
|
while (ilen >= (4 * sizeof(u32))) {
|
|
unsigned long addr, size;
|
|
|
|
/* XXX Use proper OF parsing code here !!! */
|
|
addr = (unsigned long)*ireg++ << 32;
|
|
ilen -= sizeof(u32);
|
|
addr |= *ireg++;
|
|
ilen -= sizeof(u32);
|
|
size = (unsigned long)*ireg++ << 32;
|
|
ilen -= sizeof(u32);
|
|
size |= *ireg++;
|
|
ilen -= sizeof(u32);
|
|
xics_map_one_cpu(*indx, addr, size);
|
|
(*indx)++;
|
|
}
|
|
}
|
|
|
|
void __init xics_init_IRQ(void)
|
|
{
|
|
struct device_node *np;
|
|
u32 indx = 0;
|
|
int found = 0;
|
|
const u32 *isize;
|
|
|
|
ppc64_boot_msg(0x20, "XICS Init");
|
|
|
|
ibm_get_xive = rtas_token("ibm,get-xive");
|
|
ibm_set_xive = rtas_token("ibm,set-xive");
|
|
ibm_int_on = rtas_token("ibm,int-on");
|
|
ibm_int_off = rtas_token("ibm,int-off");
|
|
|
|
for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
|
|
found = 1;
|
|
if (firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
of_node_put(np);
|
|
break;
|
|
}
|
|
xics_init_one_node(np, &indx);
|
|
}
|
|
if (found == 0)
|
|
return;
|
|
|
|
/* get the bit size of server numbers */
|
|
found = 0;
|
|
|
|
for_each_compatible_node(np, NULL, "ibm,ppc-xics") {
|
|
isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
|
|
|
|
if (!isize)
|
|
continue;
|
|
|
|
if (!found) {
|
|
interrupt_server_size = *isize;
|
|
found = 1;
|
|
} else if (*isize != interrupt_server_size) {
|
|
printk(KERN_WARNING "XICS: "
|
|
"mismatched ibm,interrupt-server#-size\n");
|
|
interrupt_server_size = max(*isize,
|
|
interrupt_server_size);
|
|
}
|
|
}
|
|
|
|
xics_update_irq_servers();
|
|
xics_init_host();
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
ppc_md.get_irq = xics_get_irq_lpar;
|
|
else
|
|
ppc_md.get_irq = xics_get_irq_direct;
|
|
|
|
xics_setup_cpu();
|
|
|
|
ppc64_boot_msg(0x21, "XICS Done");
|
|
}
|
|
|
|
/* Cpu startup, shutdown, and hotplug */
|
|
|
|
static void xics_set_cpu_priority(unsigned char cppr)
|
|
{
|
|
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
|
|
|
|
/*
|
|
* we only really want to set the priority when there's
|
|
* just one cppr value on the stack
|
|
*/
|
|
WARN_ON(os_cppr->index != 0);
|
|
|
|
os_cppr->stack[0] = cppr;
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
lpar_cppr_info(cppr);
|
|
else
|
|
direct_cppr_info(cppr);
|
|
iosync();
|
|
}
|
|
|
|
/* Have the calling processor join or leave the specified global queue */
|
|
static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
|
|
{
|
|
int index;
|
|
int status;
|
|
|
|
if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
|
|
return;
|
|
|
|
index = (1UL << interrupt_server_size) - 1 - gserver;
|
|
|
|
status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
|
|
|
|
WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
|
|
GLOBAL_INTERRUPT_QUEUE, index, join, status);
|
|
}
|
|
|
|
void xics_setup_cpu(void)
|
|
{
|
|
xics_set_cpu_priority(LOWEST_PRIORITY);
|
|
|
|
xics_set_cpu_giq(default_distrib_server, 1);
|
|
}
|
|
|
|
void xics_teardown_cpu(void)
|
|
{
|
|
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
|
|
int cpu = smp_processor_id();
|
|
|
|
/*
|
|
* we have to reset the cppr index to 0 because we're
|
|
* not going to return from the IPI
|
|
*/
|
|
os_cppr->index = 0;
|
|
xics_set_cpu_priority(0);
|
|
|
|
/* Clear any pending IPI request */
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
lpar_qirr_info(cpu, 0xff);
|
|
else
|
|
direct_qirr_info(cpu, 0xff);
|
|
}
|
|
|
|
void xics_kexec_teardown_cpu(int secondary)
|
|
{
|
|
xics_teardown_cpu();
|
|
|
|
/*
|
|
* we take the ipi irq but and never return so we
|
|
* need to EOI the IPI, but want to leave our priority 0
|
|
*
|
|
* should we check all the other interrupts too?
|
|
* should we be flagging idle loop instead?
|
|
* or creating some task to be scheduled?
|
|
*/
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR))
|
|
lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
|
|
else
|
|
direct_xirr_info_set((0x00 << 24) | XICS_IPI);
|
|
|
|
/*
|
|
* Some machines need to have at least one cpu in the GIQ,
|
|
* so leave the master cpu in the group.
|
|
*/
|
|
if (secondary)
|
|
xics_set_cpu_giq(default_distrib_server, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
/* Interrupts are disabled. */
|
|
void xics_migrate_irqs_away(void)
|
|
{
|
|
int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
|
|
unsigned int irq, virq;
|
|
|
|
/* If we used to be the default server, move to the new "boot_cpuid" */
|
|
if (hw_cpu == default_server)
|
|
xics_update_irq_servers();
|
|
|
|
/* Reject any interrupt that was queued to us... */
|
|
xics_set_cpu_priority(0);
|
|
|
|
/* Remove ourselves from the global interrupt queue */
|
|
xics_set_cpu_giq(default_distrib_server, 0);
|
|
|
|
/* Allow IPIs again... */
|
|
xics_set_cpu_priority(DEFAULT_PRIORITY);
|
|
|
|
for_each_irq(virq) {
|
|
struct irq_desc *desc;
|
|
int xics_status[2];
|
|
int status;
|
|
unsigned long flags;
|
|
|
|
/* We cant set affinity on ISA interrupts */
|
|
if (virq < NUM_ISA_INTERRUPTS)
|
|
continue;
|
|
if (irq_map[virq].host != xics_host)
|
|
continue;
|
|
irq = (unsigned int)irq_map[virq].hwirq;
|
|
/* We need to get IPIs still. */
|
|
if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
|
|
continue;
|
|
desc = irq_to_desc(virq);
|
|
|
|
/* We only need to migrate enabled IRQS */
|
|
if (desc == NULL || desc->chip == NULL
|
|
|| desc->action == NULL
|
|
|| desc->chip->set_affinity == NULL)
|
|
continue;
|
|
|
|
raw_spin_lock_irqsave(&desc->lock, flags);
|
|
|
|
status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
|
|
if (status) {
|
|
printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
|
|
__func__, irq, status);
|
|
goto unlock;
|
|
}
|
|
|
|
/*
|
|
* We only support delivery to all cpus or to one cpu.
|
|
* The irq has to be migrated only in the single cpu
|
|
* case.
|
|
*/
|
|
if (xics_status[0] != hw_cpu)
|
|
goto unlock;
|
|
|
|
printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
|
|
virq, cpu);
|
|
|
|
/* Reset affinity to all cpus */
|
|
cpumask_setall(irq_to_desc(virq)->affinity);
|
|
desc->chip->set_affinity(virq, cpu_all_mask);
|
|
unlock:
|
|
raw_spin_unlock_irqrestore(&desc->lock, flags);
|
|
}
|
|
}
|
|
#endif
|