linux/drivers/clk/hisilicon
Xinliang Liu c6e80ace83 clk: hi6220: Change syspll and media_syspll clk to 1.19GHz
In the bootloader of HiKey/96boards, syspll and media_syspll clk
was initialized to 1.19GHz. So, here changes it in kernel accordingly.

1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise
HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI
(74.25MHz required by standards). Closer pixel clock means better
compatibility to HDMI monitors.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org
2016-07-06 15:20:31 -07:00
..
Kconfig clk: hisilicon: add CRG driver for hi3519 soc 2016-05-06 11:13:32 -07:00
Makefile clk: hisilicon: add CRG driver for hi3519 soc 2016-05-06 11:13:32 -07:00
clk-hi3519.c clk: hisilicon: hi3519: add driver remove path and fix some issues 2016-06-30 12:35:20 -07:00
clk-hi3620.c clk: hisilicon: Remove CLK_IS_ROOT 2016-03-02 17:43:32 -08:00
clk-hi6220-stub.c clk: hisilicon: Remove CLK_IS_ROOT 2016-03-02 17:43:32 -08:00
clk-hi6220.c clk: hi6220: Change syspll and media_syspll clk to 1.19GHz 2016-07-06 15:20:31 -07:00
clk-hip04.c clk: hisilicon: Remove CLK_IS_ROOT 2016-03-02 17:43:32 -08:00
clk-hix5hd2.c clk: hisilicon: Remove CLK_IS_ROOT 2016-03-02 17:43:32 -08:00
clk.c clk: hisilicon: add error processing for hisi_clk_register_* functions 2016-06-30 12:35:11 -07:00
clk.h clk: hisilicon: add hisi_clk_unregister_* functions 2016-06-30 12:35:18 -07:00
clkdivider-hi6220.c clk: hi6220: fix missing clk.h include 2016-06-20 17:45:13 -07:00
clkgate-separated.c clk: hisilicon: Remove clk.h include 2015-07-20 10:53:06 -07:00
reset.c reset: hisilicon: change the definition of hisi_reset_init 2016-06-30 12:33:22 -07:00
reset.h reset: hisilicon: change the definition of hisi_reset_init 2016-06-30 12:33:22 -07:00