31e1391af2
Optionally obtain a lcd-supply regulator during probe and use it in __pxafb_lcd_power() to switch the power supply of LCD panels. This helps boards booted from DT to control such voltages without callbacks. Signed-off-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
206 lines
4.3 KiB
C
206 lines
4.3 KiB
C
#ifndef __PXAFB_H__
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#define __PXAFB_H__
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/*
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* linux/drivers/video/pxafb.h
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* -- Intel PXA250/210 LCD Controller Frame Buffer Device
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*
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* Copyright (C) 1999 Eric A. Thomas.
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* Copyright (C) 2004 Jean-Frederic Clere.
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* Copyright (C) 2004 Ian Campbell.
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* Copyright (C) 2004 Jeff Lackey.
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* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
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* which in turn is
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* Based on acornfb.c Copyright (C) Russell King.
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*
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* 2001-08-03: Cliff Brake <cbrake@acclent.com>
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* - ported SA1100 code to PXA
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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/* PXA LCD DMA descriptor */
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struct pxafb_dma_descriptor {
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unsigned int fdadr;
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unsigned int fsadr;
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unsigned int fidr;
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unsigned int ldcmd;
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};
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enum {
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PAL_NONE = -1,
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PAL_BASE = 0,
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PAL_OV1 = 1,
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PAL_OV2 = 2,
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PAL_MAX,
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};
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enum {
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DMA_BASE = 0,
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DMA_UPPER = 0,
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DMA_LOWER = 1,
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DMA_OV1 = 1,
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DMA_OV2_Y = 2,
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DMA_OV2_Cb = 3,
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DMA_OV2_Cr = 4,
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DMA_CURSOR = 5,
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DMA_CMD = 6,
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DMA_MAX,
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};
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/* maximum palette size - 256 entries, each 4 bytes long */
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#define PALETTE_SIZE (256 * 4)
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#define CMD_BUFF_SIZE (1024 * 50)
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/* NOTE: the palette and frame dma descriptors are doubled to allow
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* the 2nd set for branch settings (FBRx)
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*/
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struct pxafb_dma_buff {
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unsigned char palette[PAL_MAX * PALETTE_SIZE];
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uint16_t cmd_buff[CMD_BUFF_SIZE];
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struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
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struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
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};
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enum {
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OVERLAY1,
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OVERLAY2,
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};
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enum {
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OVERLAY_FORMAT_RGB = 0,
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OVERLAY_FORMAT_YUV444_PACKED,
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OVERLAY_FORMAT_YUV444_PLANAR,
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OVERLAY_FORMAT_YUV422_PLANAR,
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OVERLAY_FORMAT_YUV420_PLANAR,
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};
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#define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff)
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#define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff)
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#define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7)
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struct pxafb_layer;
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struct pxafb_layer_ops {
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void (*enable)(struct pxafb_layer *);
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void (*disable)(struct pxafb_layer *);
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void (*setup)(struct pxafb_layer *);
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};
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struct pxafb_layer {
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struct fb_info fb;
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int id;
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int registered;
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uint32_t usage;
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uint32_t control[2];
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struct pxafb_layer_ops *ops;
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void __iomem *video_mem;
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unsigned long video_mem_phys;
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size_t video_mem_size;
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struct completion branch_done;
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struct pxafb_info *fbi;
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};
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struct pxafb_info {
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struct fb_info fb;
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struct device *dev;
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struct clk *clk;
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void __iomem *mmio_base;
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struct pxafb_dma_buff *dma_buff;
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size_t dma_buff_size;
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dma_addr_t dma_buff_phys;
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dma_addr_t fdadr[DMA_MAX * 2];
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void __iomem *video_mem; /* virtual address of frame buffer */
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unsigned long video_mem_phys; /* physical address of frame buffer */
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size_t video_mem_size; /* size of the frame buffer */
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u16 * palette_cpu; /* virtual address of palette memory */
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u_int palette_size;
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u_int lccr0;
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u_int lccr3;
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u_int lccr4;
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u_int cmap_inverse:1,
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cmap_static:1,
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unused:30;
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u_int reg_lccr0;
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u_int reg_lccr1;
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u_int reg_lccr2;
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u_int reg_lccr3;
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u_int reg_lccr4;
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u_int reg_cmdcr;
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unsigned long hsync_time;
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volatile u_char state;
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volatile u_char task_state;
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struct mutex ctrlr_lock;
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wait_queue_head_t ctrlr_wait;
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struct work_struct task;
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struct completion disable_done;
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#ifdef CONFIG_FB_PXA_SMARTPANEL
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uint16_t *smart_cmds;
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size_t n_smart_cmds;
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struct completion command_done;
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struct completion refresh_done;
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struct task_struct *smart_thread;
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#endif
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#ifdef CONFIG_FB_PXA_OVERLAY
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struct pxafb_layer overlay[2];
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#endif
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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struct notifier_block freq_policy;
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#endif
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struct regulator *lcd_supply;
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bool lcd_supply_enabled;
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void (*lcd_power)(int, struct fb_var_screeninfo *);
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void (*backlight_power)(int);
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struct pxafb_mach_info *inf;
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};
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#define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
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/*
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* These are the actions for set_ctrlr_state
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*/
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#define C_DISABLE (0)
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#define C_ENABLE (1)
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#define C_DISABLE_CLKCHANGE (2)
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#define C_ENABLE_CLKCHANGE (3)
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#define C_REENABLE (4)
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#define C_DISABLE_PM (5)
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#define C_ENABLE_PM (6)
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#define C_STARTUP (7)
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#define PXA_NAME "PXA"
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/*
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* Minimum X and Y resolutions
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*/
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#define MIN_XRES 64
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#define MIN_YRES 64
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/* maximum X and Y resolutions - note these are limits from the register
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* bits length instead of the real ones
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*/
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#define MAX_XRES 1024
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#define MAX_YRES 1024
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#endif /* __PXAFB_H__ */
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