2e8685a491
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
106 lines
2.4 KiB
Plaintext
106 lines
2.4 KiB
Plaintext
/*
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* MPC8536DS Device Tree Source (36-bit address map)
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*
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/mpc8536si-pre.dtsi"
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/ {
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model = "fsl,mpc8536ds";
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compatible = "fsl,mpc8536ds";
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8536@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0 0 0>; // Filled by U-Boot
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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};
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board_soc: soc: soc@fffe00000 {
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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};
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pci0: pci@ffe08000 {
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reg = <0xf 0xffe08000 0 0x1000>;
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ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
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0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 J17 Slot 1 */
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0x8800 0 0 1 &mpic 1 1 0 0
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0x8800 0 0 2 &mpic 2 1 0 0
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0x8800 0 0 3 &mpic 3 1 0 0
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0x8800 0 0 4 &mpic 4 1 0 0>;
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};
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pci1: pcie@ffe09000 {
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reg = <0xf 0xffe09000 0 0x1000>;
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ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
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0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xf8000000
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0x02000000 0 0xf8000000
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0 0x08000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci2: pcie@fffe0a000 {
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reg = <0xf 0xffe0a000 0 0x1000>;
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ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
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0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xf8000000
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0x02000000 0 0xf8000000
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0 0x08000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci3: pcie@fffe0b000 {
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reg = <0xf 0xffe0b000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
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0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00100000>;
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};
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};
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};
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/include/ "fsl/mpc8536si-post.dtsi"
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/include/ "mpc8536ds.dtsi"
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