1363 lines
37 KiB
C
1363 lines
37 KiB
C
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eugeni Dodonov <eugeni.dodonov@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "intel_drv.h"
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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
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* them for both DP and FDI transports, allowing those ports to
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* automatically adapt to HDMI connections as well
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*/
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static const u32 hsw_ddi_translations_dp[] = {
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0x00FFFFFF, 0x0006000E, /* DP parameters */
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0x00D75FFF, 0x0005000A,
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0x00C30FFF, 0x00040006,
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0x80AAAFFF, 0x000B0000,
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0x00FFFFFF, 0x0005000A,
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0x00D75FFF, 0x000C0004,
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0x80C30FFF, 0x000B0000,
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0x00FFFFFF, 0x00040006,
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0x80D75FFF, 0x000B0000,
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0x00FFFFFF, 0x00040006 /* HDMI parameters */
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};
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static const u32 hsw_ddi_translations_fdi[] = {
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0x00FFFFFF, 0x0007000E, /* FDI parameters */
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0x00D75FFF, 0x000F000A,
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0x00C30FFF, 0x00060006,
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0x00AAAFFF, 0x001E0000,
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0x00FFFFFF, 0x000F000A,
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0x00D75FFF, 0x00160004,
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0x00C30FFF, 0x001E0000,
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0x00FFFFFF, 0x00060006,
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0x00D75FFF, 0x001E0000,
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0x00FFFFFF, 0x00040006 /* HDMI parameters */
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};
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static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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int type = intel_encoder->type;
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if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
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type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(encoder);
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return intel_dig_port->port;
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} else if (type == INTEL_OUTPUT_ANALOG) {
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return PORT_E;
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} else {
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DRM_ERROR("Invalid DDI encoder type %d\n", type);
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BUG();
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}
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}
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/* On Haswell, DDI port buffers must be programmed with correct values
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* in advance. The buffer values are different for FDI and DP modes,
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* but the HDMI/DVI fields are shared among those. So we program the DDI
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* in either FDI or DP modes only, as HDMI connections will work with both
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* of those
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*/
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static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg;
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int i;
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const u32 *ddi_translations = (port == PORT_E) ?
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hsw_ddi_translations_fdi :
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hsw_ddi_translations_dp;
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for (i = 0, reg = DDI_BUF_TRANS(port);
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i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
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I915_WRITE(reg, ddi_translations[i]);
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reg += 4;
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}
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}
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/* Program DDI buffers translations for DP. By default, program ports A-D in DP
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* mode and port E for FDI.
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*/
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void intel_prepare_ddi(struct drm_device *dev)
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{
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int port;
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if (!HAS_DDI(dev))
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return;
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for (port = PORT_A; port <= PORT_E; port++)
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intel_prepare_ddi_buffers(dev, port);
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}
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static const long hsw_ddi_buf_ctl_values[] = {
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DDI_BUF_EMP_400MV_0DB_HSW,
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DDI_BUF_EMP_400MV_3_5DB_HSW,
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DDI_BUF_EMP_400MV_6DB_HSW,
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DDI_BUF_EMP_400MV_9_5DB_HSW,
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DDI_BUF_EMP_600MV_0DB_HSW,
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DDI_BUF_EMP_600MV_3_5DB_HSW,
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DDI_BUF_EMP_600MV_6DB_HSW,
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DDI_BUF_EMP_800MV_0DB_HSW,
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DDI_BUF_EMP_800MV_3_5DB_HSW
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};
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static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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enum port port)
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{
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uint32_t reg = DDI_BUF_CTL(port);
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int i;
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for (i = 0; i < 8; i++) {
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udelay(1);
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if (I915_READ(reg) & DDI_BUF_IS_IDLE)
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return;
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}
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DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
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}
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/* Starting with Haswell, different DDI ports can work in FDI mode for
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* connection to the PCH-located connectors. For this, it is necessary to train
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* both the DDI port and PCH receiver for the desired DDI buffer settings.
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*
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* The recommended port to work in FDI mode is DDI E, which we use here. Also,
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* please note that when FDI mode is active on DDI E, it shares 2 lines with
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* DDI A (which is used for eDP)
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*/
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void hsw_fdi_link_train(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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u32 temp, i, rx_ctl_val;
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/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
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* mode set "sequence for CRT port" document:
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* - TP1 to TP2 time with the default value
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* - FDI delay to 90h
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*
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* WaFDIAutoLinkSetTimingOverrride:hsw
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*/
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I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
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FDI_RX_PWRDN_LANE0_VAL(2) |
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FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
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/* Enable the PCH Receiver FDI PLL */
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rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
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FDI_RX_PLL_ENABLE |
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FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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udelay(220);
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/* Switch from Rawclk to PCDclk */
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rx_ctl_val |= FDI_PCDCLK;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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/* Configure Port Clock Select */
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I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
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/* Start the training iterating through available voltages and emphasis,
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* testing each value twice. */
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for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
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/* Configure DP_TP_CTL with auto-training */
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I915_WRITE(DP_TP_CTL(PORT_E),
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DP_TP_CTL_FDI_AUTOTRAIN |
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DP_TP_CTL_ENHANCED_FRAME_ENABLE |
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DP_TP_CTL_LINK_TRAIN_PAT1 |
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DP_TP_CTL_ENABLE);
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/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
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* DDI E does not support port reversal, the functionality is
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* achieved on the PCH side in FDI_RX_CTL, so no need to set the
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* port reversal bit */
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I915_WRITE(DDI_BUF_CTL(PORT_E),
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DDI_BUF_CTL_ENABLE |
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((intel_crtc->config.fdi_lanes - 1) << 1) |
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hsw_ddi_buf_ctl_values[i / 2]);
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POSTING_READ(DDI_BUF_CTL(PORT_E));
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udelay(600);
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/* Program PCH FDI Receiver TU */
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I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
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/* Enable PCH FDI Receiver with auto-training */
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rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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/* Wait for FDI receiver lane calibration */
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udelay(30);
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/* Unset FDI_RX_MISC pwrdn lanes */
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temp = I915_READ(_FDI_RXA_MISC);
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temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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I915_WRITE(_FDI_RXA_MISC, temp);
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POSTING_READ(_FDI_RXA_MISC);
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/* Wait for FDI auto training time */
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udelay(5);
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temp = I915_READ(DP_TP_STATUS(PORT_E));
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if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
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DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
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/* Enable normal pixel sending for FDI */
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I915_WRITE(DP_TP_CTL(PORT_E),
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DP_TP_CTL_FDI_AUTOTRAIN |
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DP_TP_CTL_LINK_TRAIN_NORMAL |
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DP_TP_CTL_ENHANCED_FRAME_ENABLE |
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DP_TP_CTL_ENABLE);
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return;
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}
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temp = I915_READ(DDI_BUF_CTL(PORT_E));
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temp &= ~DDI_BUF_CTL_ENABLE;
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I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
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POSTING_READ(DDI_BUF_CTL(PORT_E));
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/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
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temp = I915_READ(DP_TP_CTL(PORT_E));
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temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
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temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
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I915_WRITE(DP_TP_CTL(PORT_E), temp);
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POSTING_READ(DP_TP_CTL(PORT_E));
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intel_wait_ddi_buf_idle(dev_priv, PORT_E);
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rx_ctl_val &= ~FDI_RX_ENABLE;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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/* Reset FDI_RX_MISC pwrdn lanes */
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temp = I915_READ(_FDI_RXA_MISC);
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temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
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I915_WRITE(_FDI_RXA_MISC, temp);
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POSTING_READ(_FDI_RXA_MISC);
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}
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DRM_ERROR("FDI link training failed!\n");
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}
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static void intel_ddi_mode_set(struct intel_encoder *encoder)
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{
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struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
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int port = intel_ddi_get_encoder_port(encoder);
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int pipe = crtc->pipe;
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int type = encoder->type;
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struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
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DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
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port_name(port), pipe_name(pipe));
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crtc->eld_vld = false;
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if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
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struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
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struct intel_digital_port *intel_dig_port =
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enc_to_dig_port(&encoder->base);
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intel_dp->DP = intel_dig_port->saved_port_bits |
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DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
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intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
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if (intel_dp->has_audio) {
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DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
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pipe_name(crtc->pipe));
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/* write eld */
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DRM_DEBUG_DRIVER("DP audio: write eld information\n");
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intel_write_eld(&encoder->base, adjusted_mode);
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}
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intel_dp_init_link_config(intel_dp);
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} else if (type == INTEL_OUTPUT_HDMI) {
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
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if (intel_hdmi->has_audio) {
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/* Proper support for digital audio needs a new logic
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* and a new set of registers, so we leave it for future
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* patch bombing.
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*/
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DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
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pipe_name(crtc->pipe));
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/* write eld */
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DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
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intel_write_eld(&encoder->base, adjusted_mode);
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}
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intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
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}
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}
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static struct intel_encoder *
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intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *intel_encoder, *ret = NULL;
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int num_encoders = 0;
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for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
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ret = intel_encoder;
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num_encoders++;
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}
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if (num_encoders != 1)
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WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
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pipe_name(intel_crtc->pipe));
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BUG_ON(ret == NULL);
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return ret;
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}
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void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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uint32_t val;
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switch (intel_crtc->ddi_pll_sel) {
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case PORT_CLK_SEL_SPLL:
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plls->spll_refcount--;
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if (plls->spll_refcount == 0) {
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DRM_DEBUG_KMS("Disabling SPLL\n");
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val = I915_READ(SPLL_CTL);
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WARN_ON(!(val & SPLL_PLL_ENABLE));
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I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
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POSTING_READ(SPLL_CTL);
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}
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break;
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case PORT_CLK_SEL_WRPLL1:
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plls->wrpll1_refcount--;
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if (plls->wrpll1_refcount == 0) {
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DRM_DEBUG_KMS("Disabling WRPLL 1\n");
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val = I915_READ(WRPLL_CTL1);
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WARN_ON(!(val & WRPLL_PLL_ENABLE));
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I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL1);
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}
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break;
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case PORT_CLK_SEL_WRPLL2:
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plls->wrpll2_refcount--;
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if (plls->wrpll2_refcount == 0) {
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DRM_DEBUG_KMS("Disabling WRPLL 2\n");
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val = I915_READ(WRPLL_CTL2);
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WARN_ON(!(val & WRPLL_PLL_ENABLE));
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I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL2);
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}
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break;
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}
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WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
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WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
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WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
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intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
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}
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#define LC_FREQ 2700
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#define LC_FREQ_2K (LC_FREQ * 2000)
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#define P_MIN 2
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#define P_MAX 64
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#define P_INC 2
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|
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/* Constraints for PLL good behavior */
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#define REF_MIN 48
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#define REF_MAX 400
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#define VCO_MIN 2400
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#define VCO_MAX 4800
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#define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
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|
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struct wrpll_rnp {
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unsigned p, n2, r2;
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};
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|
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static unsigned wrpll_get_budget_for_freq(int clock)
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{
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unsigned budget;
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|
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switch (clock) {
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case 25175000:
|
|
case 25200000:
|
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case 27000000:
|
|
case 27027000:
|
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case 37762500:
|
|
case 37800000:
|
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case 40500000:
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case 40541000:
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case 54000000:
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case 54054000:
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case 59341000:
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case 59400000:
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case 72000000:
|
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case 74176000:
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case 74250000:
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case 81000000:
|
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case 81081000:
|
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case 89012000:
|
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case 89100000:
|
|
case 108000000:
|
|
case 108108000:
|
|
case 111264000:
|
|
case 111375000:
|
|
case 148352000:
|
|
case 148500000:
|
|
case 162000000:
|
|
case 162162000:
|
|
case 222525000:
|
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case 222750000:
|
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case 296703000:
|
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case 297000000:
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budget = 0;
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break;
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case 233500000:
|
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case 245250000:
|
|
case 247750000:
|
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case 253250000:
|
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case 298000000:
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budget = 1500;
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break;
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case 169128000:
|
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case 169500000:
|
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case 179500000:
|
|
case 202000000:
|
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budget = 2000;
|
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break;
|
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case 256250000:
|
|
case 262500000:
|
|
case 270000000:
|
|
case 272500000:
|
|
case 273750000:
|
|
case 280750000:
|
|
case 281250000:
|
|
case 286000000:
|
|
case 291750000:
|
|
budget = 4000;
|
|
break;
|
|
case 267250000:
|
|
case 268500000:
|
|
budget = 5000;
|
|
break;
|
|
default:
|
|
budget = 1000;
|
|
break;
|
|
}
|
|
|
|
return budget;
|
|
}
|
|
|
|
static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
|
|
unsigned r2, unsigned n2, unsigned p,
|
|
struct wrpll_rnp *best)
|
|
{
|
|
uint64_t a, b, c, d, diff, diff_best;
|
|
|
|
/* No best (r,n,p) yet */
|
|
if (best->p == 0) {
|
|
best->p = p;
|
|
best->n2 = n2;
|
|
best->r2 = r2;
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
|
|
* freq2k.
|
|
*
|
|
* delta = 1e6 *
|
|
* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
|
|
* freq2k;
|
|
*
|
|
* and we would like delta <= budget.
|
|
*
|
|
* If the discrepancy is above the PPM-based budget, always prefer to
|
|
* improve upon the previous solution. However, if you're within the
|
|
* budget, try to maximize Ref * VCO, that is N / (P * R^2).
|
|
*/
|
|
a = freq2k * budget * p * r2;
|
|
b = freq2k * budget * best->p * best->r2;
|
|
diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
|
|
diff_best = ABS_DIFF((freq2k * best->p * best->r2),
|
|
(LC_FREQ_2K * best->n2));
|
|
c = 1000000 * diff;
|
|
d = 1000000 * diff_best;
|
|
|
|
if (a < c && b < d) {
|
|
/* If both are above the budget, pick the closer */
|
|
if (best->p * best->r2 * diff < p * r2 * diff_best) {
|
|
best->p = p;
|
|
best->n2 = n2;
|
|
best->r2 = r2;
|
|
}
|
|
} else if (a >= c && b < d) {
|
|
/* If A is below the threshold but B is above it? Update. */
|
|
best->p = p;
|
|
best->n2 = n2;
|
|
best->r2 = r2;
|
|
} else if (a >= c && b >= d) {
|
|
/* Both are below the limit, so pick the higher n2/(r2*r2) */
|
|
if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
|
|
best->p = p;
|
|
best->n2 = n2;
|
|
best->r2 = r2;
|
|
}
|
|
}
|
|
/* Otherwise a < c && b >= d, do nothing */
|
|
}
|
|
|
|
static void
|
|
intel_ddi_calculate_wrpll(int clock /* in Hz */,
|
|
unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
|
|
{
|
|
uint64_t freq2k;
|
|
unsigned p, n2, r2;
|
|
struct wrpll_rnp best = { 0, 0, 0 };
|
|
unsigned budget;
|
|
|
|
freq2k = clock / 100;
|
|
|
|
budget = wrpll_get_budget_for_freq(clock);
|
|
|
|
/* Special case handling for 540 pixel clock: bypass WR PLL entirely
|
|
* and directly pass the LC PLL to it. */
|
|
if (freq2k == 5400000) {
|
|
*n2_out = 2;
|
|
*p_out = 1;
|
|
*r2_out = 2;
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Ref = LC_FREQ / R, where Ref is the actual reference input seen by
|
|
* the WR PLL.
|
|
*
|
|
* We want R so that REF_MIN <= Ref <= REF_MAX.
|
|
* Injecting R2 = 2 * R gives:
|
|
* REF_MAX * r2 > LC_FREQ * 2 and
|
|
* REF_MIN * r2 < LC_FREQ * 2
|
|
*
|
|
* Which means the desired boundaries for r2 are:
|
|
* LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
|
|
*
|
|
*/
|
|
for (r2 = LC_FREQ * 2 / REF_MAX + 1;
|
|
r2 <= LC_FREQ * 2 / REF_MIN;
|
|
r2++) {
|
|
|
|
/*
|
|
* VCO = N * Ref, that is: VCO = N * LC_FREQ / R
|
|
*
|
|
* Once again we want VCO_MIN <= VCO <= VCO_MAX.
|
|
* Injecting R2 = 2 * R and N2 = 2 * N, we get:
|
|
* VCO_MAX * r2 > n2 * LC_FREQ and
|
|
* VCO_MIN * r2 < n2 * LC_FREQ)
|
|
*
|
|
* Which means the desired boundaries for n2 are:
|
|
* VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
|
|
*/
|
|
for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
|
|
n2 <= VCO_MAX * r2 / LC_FREQ;
|
|
n2++) {
|
|
|
|
for (p = P_MIN; p <= P_MAX; p += P_INC)
|
|
wrpll_update_rnp(freq2k, budget,
|
|
r2, n2, p, &best);
|
|
}
|
|
}
|
|
|
|
*n2_out = best.n2;
|
|
*p_out = best.p;
|
|
*r2_out = best.r2;
|
|
|
|
DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
|
|
clock, *p_out, *n2_out, *r2_out);
|
|
}
|
|
|
|
bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
|
|
{
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
|
|
int type = intel_encoder->type;
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
uint32_t reg, val;
|
|
int clock = intel_crtc->config.port_clock;
|
|
|
|
/* TODO: reuse PLLs when possible (compare values) */
|
|
|
|
intel_ddi_put_crtc_pll(crtc);
|
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
switch (intel_dp->link_bw) {
|
|
case DP_LINK_BW_1_62:
|
|
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
|
|
break;
|
|
case DP_LINK_BW_2_7:
|
|
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
|
|
break;
|
|
case DP_LINK_BW_5_4:
|
|
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
|
|
break;
|
|
default:
|
|
DRM_ERROR("Link bandwidth %d unsupported\n",
|
|
intel_dp->link_bw);
|
|
return false;
|
|
}
|
|
|
|
/* We don't need to turn any PLL on because we'll use LCPLL. */
|
|
return true;
|
|
|
|
} else if (type == INTEL_OUTPUT_HDMI) {
|
|
unsigned p, n2, r2;
|
|
|
|
if (plls->wrpll1_refcount == 0) {
|
|
DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
|
|
pipe_name(pipe));
|
|
plls->wrpll1_refcount++;
|
|
reg = WRPLL_CTL1;
|
|
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
|
|
} else if (plls->wrpll2_refcount == 0) {
|
|
DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
|
|
pipe_name(pipe));
|
|
plls->wrpll2_refcount++;
|
|
reg = WRPLL_CTL2;
|
|
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
|
|
} else {
|
|
DRM_ERROR("No WRPLLs available!\n");
|
|
return false;
|
|
}
|
|
|
|
WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
|
|
"WRPLL already enabled\n");
|
|
|
|
intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
|
|
|
|
val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
|
|
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
|
|
WRPLL_DIVIDER_POST(p);
|
|
|
|
} else if (type == INTEL_OUTPUT_ANALOG) {
|
|
if (plls->spll_refcount == 0) {
|
|
DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
|
|
pipe_name(pipe));
|
|
plls->spll_refcount++;
|
|
reg = SPLL_CTL;
|
|
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
|
|
} else {
|
|
DRM_ERROR("SPLL already in use\n");
|
|
return false;
|
|
}
|
|
|
|
WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
|
|
"SPLL already enabled\n");
|
|
|
|
val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
|
|
|
|
} else {
|
|
WARN(1, "Invalid DDI encoder type %d\n", type);
|
|
return false;
|
|
}
|
|
|
|
I915_WRITE(reg, val);
|
|
udelay(20);
|
|
|
|
return true;
|
|
}
|
|
|
|
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
|
|
int type = intel_encoder->type;
|
|
uint32_t temp;
|
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
|
|
|
|
temp = TRANS_MSA_SYNC_CLK;
|
|
switch (intel_crtc->config.pipe_bpp) {
|
|
case 18:
|
|
temp |= TRANS_MSA_6_BPC;
|
|
break;
|
|
case 24:
|
|
temp |= TRANS_MSA_8_BPC;
|
|
break;
|
|
case 30:
|
|
temp |= TRANS_MSA_10_BPC;
|
|
break;
|
|
case 36:
|
|
temp |= TRANS_MSA_12_BPC;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
|
|
}
|
|
}
|
|
|
|
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
|
|
{
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
int type = intel_encoder->type;
|
|
uint32_t temp;
|
|
|
|
/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
|
|
temp = TRANS_DDI_FUNC_ENABLE;
|
|
temp |= TRANS_DDI_SELECT_PORT(port);
|
|
|
|
switch (intel_crtc->config.pipe_bpp) {
|
|
case 18:
|
|
temp |= TRANS_DDI_BPC_6;
|
|
break;
|
|
case 24:
|
|
temp |= TRANS_DDI_BPC_8;
|
|
break;
|
|
case 30:
|
|
temp |= TRANS_DDI_BPC_10;
|
|
break;
|
|
case 36:
|
|
temp |= TRANS_DDI_BPC_12;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
|
|
temp |= TRANS_DDI_PVSYNC;
|
|
if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
|
|
temp |= TRANS_DDI_PHSYNC;
|
|
|
|
if (cpu_transcoder == TRANSCODER_EDP) {
|
|
switch (pipe) {
|
|
case PIPE_A:
|
|
/* Can only use the always-on power well for eDP when
|
|
* not using the panel fitter, and when not using motion
|
|
* blur mitigation (which we don't support). */
|
|
if (intel_crtc->config.pch_pfit.size)
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
|
|
else
|
|
temp |= TRANS_DDI_EDP_INPUT_A_ON;
|
|
break;
|
|
case PIPE_B:
|
|
temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
|
|
break;
|
|
case PIPE_C:
|
|
temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
|
|
break;
|
|
default:
|
|
BUG();
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
|
|
if (intel_hdmi->has_hdmi_sink)
|
|
temp |= TRANS_DDI_MODE_SELECT_HDMI;
|
|
else
|
|
temp |= TRANS_DDI_MODE_SELECT_DVI;
|
|
|
|
} else if (type == INTEL_OUTPUT_ANALOG) {
|
|
temp |= TRANS_DDI_MODE_SELECT_FDI;
|
|
temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
|
|
|
|
} else if (type == INTEL_OUTPUT_DISPLAYPORT ||
|
|
type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
temp |= TRANS_DDI_MODE_SELECT_DP_SST;
|
|
|
|
temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
|
|
} else {
|
|
WARN(1, "Invalid encoder type %d for pipe %c\n",
|
|
intel_encoder->type, pipe_name(pipe));
|
|
}
|
|
|
|
I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
|
|
}
|
|
|
|
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
|
|
enum transcoder cpu_transcoder)
|
|
{
|
|
uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
|
|
uint32_t val = I915_READ(reg);
|
|
|
|
val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
|
|
val |= TRANS_DDI_PORT_NONE;
|
|
I915_WRITE(reg, val);
|
|
}
|
|
|
|
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
|
|
{
|
|
struct drm_device *dev = intel_connector->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_encoder *intel_encoder = intel_connector->encoder;
|
|
int type = intel_connector->base.connector_type;
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
enum pipe pipe = 0;
|
|
enum transcoder cpu_transcoder;
|
|
uint32_t tmp;
|
|
|
|
if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
|
|
return false;
|
|
|
|
if (port == PORT_A)
|
|
cpu_transcoder = TRANSCODER_EDP;
|
|
else
|
|
cpu_transcoder = (enum transcoder) pipe;
|
|
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
|
|
switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
|
|
case TRANS_DDI_MODE_SELECT_HDMI:
|
|
case TRANS_DDI_MODE_SELECT_DVI:
|
|
return (type == DRM_MODE_CONNECTOR_HDMIA);
|
|
|
|
case TRANS_DDI_MODE_SELECT_DP_SST:
|
|
if (type == DRM_MODE_CONNECTOR_eDP)
|
|
return true;
|
|
case TRANS_DDI_MODE_SELECT_DP_MST:
|
|
return (type == DRM_MODE_CONNECTOR_DisplayPort);
|
|
|
|
case TRANS_DDI_MODE_SELECT_FDI:
|
|
return (type == DRM_MODE_CONNECTOR_VGA);
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
|
|
enum pipe *pipe)
|
|
{
|
|
struct drm_device *dev = encoder->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
enum port port = intel_ddi_get_encoder_port(encoder);
|
|
u32 tmp;
|
|
int i;
|
|
|
|
tmp = I915_READ(DDI_BUF_CTL(port));
|
|
|
|
if (!(tmp & DDI_BUF_CTL_ENABLE))
|
|
return false;
|
|
|
|
if (port == PORT_A) {
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
|
|
|
|
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
|
|
case TRANS_DDI_EDP_INPUT_A_ON:
|
|
case TRANS_DDI_EDP_INPUT_A_ONOFF:
|
|
*pipe = PIPE_A;
|
|
break;
|
|
case TRANS_DDI_EDP_INPUT_B_ONOFF:
|
|
*pipe = PIPE_B;
|
|
break;
|
|
case TRANS_DDI_EDP_INPUT_C_ONOFF:
|
|
*pipe = PIPE_C;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
} else {
|
|
for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
|
|
tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
|
|
|
|
if ((tmp & TRANS_DDI_PORT_MASK)
|
|
== TRANS_DDI_SELECT_PORT(port)) {
|
|
*pipe = i;
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
|
|
|
|
return false;
|
|
}
|
|
|
|
static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
|
|
enum pipe pipe)
|
|
{
|
|
uint32_t temp, ret;
|
|
enum port port = I915_MAX_PORTS;
|
|
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
|
|
pipe);
|
|
int i;
|
|
|
|
if (cpu_transcoder == TRANSCODER_EDP) {
|
|
port = PORT_A;
|
|
} else {
|
|
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
temp &= TRANS_DDI_PORT_MASK;
|
|
|
|
for (i = PORT_B; i <= PORT_E; i++)
|
|
if (temp == TRANS_DDI_SELECT_PORT(i))
|
|
port = i;
|
|
}
|
|
|
|
if (port == I915_MAX_PORTS) {
|
|
WARN(1, "Pipe %c enabled on an unknown port\n",
|
|
pipe_name(pipe));
|
|
ret = PORT_CLK_SEL_NONE;
|
|
} else {
|
|
ret = I915_READ(PORT_CLK_SEL(port));
|
|
DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
|
|
"0x%08x\n", pipe_name(pipe), port_name(port),
|
|
ret);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
enum pipe pipe;
|
|
struct intel_crtc *intel_crtc;
|
|
|
|
for_each_pipe(pipe) {
|
|
intel_crtc =
|
|
to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
|
|
|
|
if (!intel_crtc->active)
|
|
continue;
|
|
|
|
intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
|
|
pipe);
|
|
|
|
switch (intel_crtc->ddi_pll_sel) {
|
|
case PORT_CLK_SEL_SPLL:
|
|
dev_priv->ddi_plls.spll_refcount++;
|
|
break;
|
|
case PORT_CLK_SEL_WRPLL1:
|
|
dev_priv->ddi_plls.wrpll1_refcount++;
|
|
break;
|
|
case PORT_CLK_SEL_WRPLL2:
|
|
dev_priv->ddi_plls.wrpll2_refcount++;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
|
|
{
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
|
|
|
|
if (cpu_transcoder != TRANSCODER_EDP)
|
|
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
|
|
TRANS_CLK_SEL_PORT(port));
|
|
}
|
|
|
|
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
|
|
{
|
|
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
|
|
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
|
|
|
|
if (cpu_transcoder != TRANSCODER_EDP)
|
|
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
|
|
TRANS_CLK_SEL_DISABLED);
|
|
}
|
|
|
|
static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
int type = intel_encoder->type;
|
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
|
ironlake_edp_panel_on(intel_dp);
|
|
ironlake_edp_panel_vdd_off(intel_dp, true);
|
|
}
|
|
|
|
WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
|
|
I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
|
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
|
|
intel_dp_start_link_train(intel_dp);
|
|
intel_dp_complete_link_train(intel_dp);
|
|
if (port != PORT_A)
|
|
intel_dp_stop_link_train(intel_dp);
|
|
}
|
|
}
|
|
|
|
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
int type = intel_encoder->type;
|
|
uint32_t val;
|
|
bool wait = false;
|
|
|
|
val = I915_READ(DDI_BUF_CTL(port));
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
I915_WRITE(DDI_BUF_CTL(port), val);
|
|
wait = true;
|
|
}
|
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
if (wait)
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
ironlake_edp_panel_vdd_on(intel_dp);
|
|
ironlake_edp_panel_off(intel_dp);
|
|
}
|
|
|
|
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
|
|
}
|
|
|
|
static void intel_enable_ddi(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
int pipe = intel_crtc->pipe;
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
enum port port = intel_ddi_get_encoder_port(intel_encoder);
|
|
int type = intel_encoder->type;
|
|
uint32_t tmp;
|
|
|
|
if (type == INTEL_OUTPUT_HDMI) {
|
|
struct intel_digital_port *intel_dig_port =
|
|
enc_to_dig_port(encoder);
|
|
|
|
/* In HDMI/DVI mode, the port width, and swing/emphasis values
|
|
* are ignored so nothing special needs to be done besides
|
|
* enabling the port.
|
|
*/
|
|
I915_WRITE(DDI_BUF_CTL(port),
|
|
intel_dig_port->saved_port_bits |
|
|
DDI_BUF_CTL_ENABLE);
|
|
} else if (type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
if (port == PORT_A)
|
|
intel_dp_stop_link_train(intel_dp);
|
|
|
|
ironlake_edp_backlight_on(intel_dp);
|
|
intel_edp_psr_enable(intel_dp);
|
|
}
|
|
|
|
if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
|
|
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
|
|
tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
|
|
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
|
|
}
|
|
}
|
|
|
|
static void intel_disable_ddi(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct drm_encoder *encoder = &intel_encoder->base;
|
|
struct drm_crtc *crtc = encoder->crtc;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
|
int pipe = intel_crtc->pipe;
|
|
int type = intel_encoder->type;
|
|
struct drm_device *dev = encoder->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
uint32_t tmp;
|
|
|
|
if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
|
|
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
|
|
tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
|
|
(pipe * 4));
|
|
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
|
|
}
|
|
|
|
if (type == INTEL_OUTPUT_EDP) {
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
intel_edp_psr_disable(intel_dp);
|
|
ironlake_edp_backlight_off(intel_dp);
|
|
}
|
|
}
|
|
|
|
int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
|
|
{
|
|
uint32_t lcpll = I915_READ(LCPLL_CTL);
|
|
|
|
if (lcpll & LCPLL_CD_SOURCE_FCLK)
|
|
return 800000;
|
|
else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
|
|
return 450000;
|
|
else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
|
|
return 450000;
|
|
else if (IS_ULT(dev_priv->dev))
|
|
return 337500;
|
|
else
|
|
return 540000;
|
|
}
|
|
|
|
void intel_ddi_pll_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
uint32_t val = I915_READ(LCPLL_CTL);
|
|
|
|
/* The LCPLL register should be turned on by the BIOS. For now let's
|
|
* just check its state and print errors in case something is wrong.
|
|
* Don't even try to turn it on.
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
|
|
intel_ddi_get_cdclk_freq(dev_priv));
|
|
|
|
if (val & LCPLL_CD_SOURCE_FCLK)
|
|
DRM_ERROR("CDCLK source is not LCPLL\n");
|
|
|
|
if (val & LCPLL_PLL_DISABLE)
|
|
DRM_ERROR("LCPLL is disabled\n");
|
|
}
|
|
|
|
void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
|
|
{
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
enum port port = intel_dig_port->port;
|
|
uint32_t val;
|
|
bool wait = false;
|
|
|
|
if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
|
|
val = I915_READ(DDI_BUF_CTL(port));
|
|
if (val & DDI_BUF_CTL_ENABLE) {
|
|
val &= ~DDI_BUF_CTL_ENABLE;
|
|
I915_WRITE(DDI_BUF_CTL(port), val);
|
|
wait = true;
|
|
}
|
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
|
|
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
POSTING_READ(DP_TP_CTL(port));
|
|
|
|
if (wait)
|
|
intel_wait_ddi_buf_idle(dev_priv, port);
|
|
}
|
|
|
|
val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
|
|
DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
|
|
if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
|
|
val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
POSTING_READ(DP_TP_CTL(port));
|
|
|
|
intel_dp->DP |= DDI_BUF_CTL_ENABLE;
|
|
I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
|
|
POSTING_READ(DDI_BUF_CTL(port));
|
|
|
|
udelay(600);
|
|
}
|
|
|
|
void intel_ddi_fdi_disable(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_i915_private *dev_priv = crtc->dev->dev_private;
|
|
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
|
|
uint32_t val;
|
|
|
|
intel_ddi_post_disable(intel_encoder);
|
|
|
|
val = I915_READ(_FDI_RXA_CTL);
|
|
val &= ~FDI_RX_ENABLE;
|
|
I915_WRITE(_FDI_RXA_CTL, val);
|
|
|
|
val = I915_READ(_FDI_RXA_MISC);
|
|
val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
|
|
val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
|
|
I915_WRITE(_FDI_RXA_MISC, val);
|
|
|
|
val = I915_READ(_FDI_RXA_CTL);
|
|
val &= ~FDI_PCDCLK;
|
|
I915_WRITE(_FDI_RXA_CTL, val);
|
|
|
|
val = I915_READ(_FDI_RXA_CTL);
|
|
val &= ~FDI_RX_PLL_ENABLE;
|
|
I915_WRITE(_FDI_RXA_CTL, val);
|
|
}
|
|
|
|
static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
|
int type = intel_encoder->type;
|
|
|
|
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
|
|
intel_dp_check_link_status(intel_dp);
|
|
}
|
|
|
|
static void intel_ddi_get_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_config *pipe_config)
|
|
{
|
|
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
|
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
|
|
u32 temp, flags = 0;
|
|
|
|
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
|
|
if (temp & TRANS_DDI_PHSYNC)
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
else
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
|
if (temp & TRANS_DDI_PVSYNC)
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
else
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
pipe_config->adjusted_mode.flags |= flags;
|
|
}
|
|
|
|
static void intel_ddi_destroy(struct drm_encoder *encoder)
|
|
{
|
|
/* HDMI has nothing special to destroy, so we can go with this. */
|
|
intel_dp_encoder_destroy(encoder);
|
|
}
|
|
|
|
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_config *pipe_config)
|
|
{
|
|
int type = encoder->type;
|
|
int port = intel_ddi_get_encoder_port(encoder);
|
|
|
|
WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
|
|
|
|
if (port == PORT_A)
|
|
pipe_config->cpu_transcoder = TRANSCODER_EDP;
|
|
|
|
if (type == INTEL_OUTPUT_HDMI)
|
|
return intel_hdmi_compute_config(encoder, pipe_config);
|
|
else
|
|
return intel_dp_compute_config(encoder, pipe_config);
|
|
}
|
|
|
|
static const struct drm_encoder_funcs intel_ddi_funcs = {
|
|
.destroy = intel_ddi_destroy,
|
|
};
|
|
|
|
void intel_ddi_init(struct drm_device *dev, enum port port)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_digital_port *intel_dig_port;
|
|
struct intel_encoder *intel_encoder;
|
|
struct drm_encoder *encoder;
|
|
struct intel_connector *hdmi_connector = NULL;
|
|
struct intel_connector *dp_connector = NULL;
|
|
|
|
intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
|
|
if (!intel_dig_port)
|
|
return;
|
|
|
|
dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
|
|
if (!dp_connector) {
|
|
kfree(intel_dig_port);
|
|
return;
|
|
}
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
encoder = &intel_encoder->base;
|
|
|
|
drm_encoder_init(dev, encoder, &intel_ddi_funcs,
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
intel_encoder->compute_config = intel_ddi_compute_config;
|
|
intel_encoder->mode_set = intel_ddi_mode_set;
|
|
intel_encoder->enable = intel_enable_ddi;
|
|
intel_encoder->pre_enable = intel_ddi_pre_enable;
|
|
intel_encoder->disable = intel_disable_ddi;
|
|
intel_encoder->post_disable = intel_ddi_post_disable;
|
|
intel_encoder->get_hw_state = intel_ddi_get_hw_state;
|
|
intel_encoder->get_config = intel_ddi_get_config;
|
|
|
|
intel_dig_port->port = port;
|
|
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
|
|
(DDI_BUF_PORT_REVERSAL |
|
|
DDI_A_4_LANES);
|
|
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
intel_encoder->cloneable = false;
|
|
intel_encoder->hot_plug = intel_ddi_hot_plug;
|
|
|
|
if (!intel_dp_init_connector(intel_dig_port, dp_connector)) {
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(intel_dig_port);
|
|
kfree(dp_connector);
|
|
return;
|
|
}
|
|
|
|
if (intel_encoder->type != INTEL_OUTPUT_EDP) {
|
|
hdmi_connector = kzalloc(sizeof(struct intel_connector),
|
|
GFP_KERNEL);
|
|
if (!hdmi_connector) {
|
|
return;
|
|
}
|
|
|
|
intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
|
|
intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
|
|
}
|
|
}
|