397 lines
11 KiB
C
397 lines
11 KiB
C
/*
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* linux/drivers/video/w100fb.c
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*
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* Corgi LCD Specific Code for ATI Imageon w100 (Wallaby)
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*
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* Copyright (C) 2005 Richard Purdie
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <asm/arch/corgi.h>
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#include <asm/mach/sharpsl_param.h>
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#include <video/w100fb.h>
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/* Register Addresses */
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#define RESCTL_ADRS 0x00
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#define PHACTRL_ADRS 0x01
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#define DUTYCTRL_ADRS 0x02
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#define POWERREG0_ADRS 0x03
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#define POWERREG1_ADRS 0x04
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#define GPOR3_ADRS 0x05
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#define PICTRL_ADRS 0x06
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#define POLCTRL_ADRS 0x07
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/* Resgister Bit Definitions */
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#define RESCTL_QVGA 0x01
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#define RESCTL_VGA 0x00
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#define POWER1_VW_ON 0x01 /* VW Supply FET ON */
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#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
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#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
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#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
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#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
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#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
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#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
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#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
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#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
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#define POWER0_COM_ON 0x08 /* COM Powewr Supply ON */
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#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
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#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
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#define POWER0_COM_OFF 0x00 /* COM Powewr Supply OFF */
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#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
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#define PICTRL_INIT_STATE 0x01
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#define PICTRL_INIOFF 0x02
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#define PICTRL_POWER_DOWN 0x04
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#define PICTRL_COM_SIGNAL_OFF 0x08
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#define PICTRL_DAC_SIGNAL_OFF 0x10
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#define POLCTRL_SYNC_POL_FALL 0x01
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#define POLCTRL_EN_POL_FALL 0x02
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#define POLCTRL_DATA_POL_FALL 0x04
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#define POLCTRL_SYNC_ACT_H 0x08
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#define POLCTRL_EN_ACT_L 0x10
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#define POLCTRL_SYNC_POL_RISE 0x00
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#define POLCTRL_EN_POL_RISE 0x00
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#define POLCTRL_DATA_POL_RISE 0x00
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#define POLCTRL_SYNC_ACT_L 0x00
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#define POLCTRL_EN_ACT_H 0x00
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#define PHACTRL_PHASE_MANUAL 0x01
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#define DEFAULT_PHAD_QVGA (9)
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#define DEFAULT_COMADJ (125)
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/*
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* This is only a psuedo I2C interface. We can't use the standard kernel
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* routines as the interface is write only. We just assume the data is acked...
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*/
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static void lcdtg_ssp_i2c_send(u8 data)
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{
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
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udelay(10);
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}
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static void lcdtg_i2c_send_bit(u8 data)
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{
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lcdtg_ssp_i2c_send(data);
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lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
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lcdtg_ssp_i2c_send(data);
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}
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static void lcdtg_i2c_send_start(u8 base)
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{
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
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lcdtg_ssp_i2c_send(base);
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}
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static void lcdtg_i2c_send_stop(u8 base)
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{
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lcdtg_ssp_i2c_send(base);
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
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lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
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}
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static void lcdtg_i2c_send_byte(u8 base, u8 data)
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{
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int i;
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for (i = 0; i < 8; i++) {
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if (data & 0x80)
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lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
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else
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lcdtg_i2c_send_bit(base);
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data <<= 1;
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}
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}
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static void lcdtg_i2c_wait_ack(u8 base)
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{
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lcdtg_i2c_send_bit(base);
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}
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static void lcdtg_set_common_voltage(u8 base_data, u8 data)
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{
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/* Set Common Voltage to M62332FP via I2C */
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lcdtg_i2c_send_start(base_data);
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lcdtg_i2c_send_byte(base_data, 0x9c);
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lcdtg_i2c_wait_ack(base_data);
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lcdtg_i2c_send_byte(base_data, 0x00);
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lcdtg_i2c_wait_ack(base_data);
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lcdtg_i2c_send_byte(base_data, data);
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lcdtg_i2c_wait_ack(base_data);
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lcdtg_i2c_send_stop(base_data);
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}
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/* Set Phase Adjuct */
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static void lcdtg_set_phadadj(struct w100fb_par *par)
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{
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int adj;
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switch(par->xres) {
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case 480:
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case 640:
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/* Setting for VGA */
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adj = sharpsl_param.phadadj;
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if (adj < 0) {
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adj = PHACTRL_PHASE_MANUAL;
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} else {
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adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
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}
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break;
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case 240:
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case 320:
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default:
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/* Setting for QVGA */
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adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
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break;
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}
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corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
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}
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static int lcd_inited;
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static void lcdtg_hw_init(struct w100fb_par *par)
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{
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if (!lcd_inited) {
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int comadj;
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/* Initialize Internal Logic & Port */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
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| PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
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| POWER0_COM_OFF | POWER0_VCC5_OFF);
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
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/* VDD(+8V), SVSS(-4V) ON */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
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mdelay(3);
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/* DAC ON */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
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| POWER0_COM_OFF | POWER0_VCC5_OFF);
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/* INIB = H, INI = L */
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/* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
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/* Set Common Voltage */
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comadj = sharpsl_param.comadj;
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if (comadj < 0)
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comadj = DEFAULT_COMADJ;
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lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
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/* VCC5 ON, DAC ON */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
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POWER0_COM_OFF | POWER0_VCC5_ON);
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/* GVSS(-8V) ON, VDD ON */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
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mdelay(2);
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/* COM SIGNAL ON (PICTL[3] = L) */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
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/* COM ON, DAC ON, VCC5_ON */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
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| POWER0_COM_ON | POWER0_VCC5_ON);
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/* VW ON, GVSS ON, VDD ON */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
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/* Signals output enable */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
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/* Set Phase Adjuct */
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lcdtg_set_phadadj(par);
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/* Initialize for Input Signals from ATI */
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corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
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| POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
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udelay(1000);
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lcd_inited=1;
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} else {
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lcdtg_set_phadadj(par);
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}
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switch(par->xres) {
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case 480:
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case 640:
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/* Set Lcd Resolution (VGA) */
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corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
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break;
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case 240:
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case 320:
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default:
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/* Set Lcd Resolution (QVGA) */
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corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
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break;
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}
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}
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static void lcdtg_suspend(struct w100fb_par *par)
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{
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/* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
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mdelay(34);
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/* (1)VW OFF */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
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/* (2)COM OFF */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
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/* (3)Set Common Voltage Bias 0V */
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lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
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/* (4)GVSS OFF */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
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/* (5)VCC5 OFF */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
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/* (6)Set PDWN, INIOFF, DACOFF */
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corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
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PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
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/* (7)DAC OFF */
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corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
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/* (8)VDD OFF */
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corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
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lcd_inited = 0;
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}
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static struct w100_tg_info corgi_lcdtg_info = {
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.change=lcdtg_hw_init,
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.suspend=lcdtg_suspend,
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.resume=lcdtg_hw_init,
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};
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/*
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* Corgi w100 Frame Buffer Device
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*/
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static struct w100_mem_info corgi_fb_mem = {
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.ext_cntl = 0x00040003,
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.sdram_mode_reg = 0x00650021,
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.ext_timing_cntl = 0x10002a4a,
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.io_cntl = 0x7ff87012,
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.size = 0x1fffff,
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};
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static struct w100_gen_regs corgi_fb_regs = {
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.lcd_format = 0x00000003,
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.lcdd_cntl1 = 0x01CC0000,
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.lcdd_cntl2 = 0x0003FFFF,
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.genlcd_cntl1 = 0x00FFFF0D,
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.genlcd_cntl2 = 0x003F3003,
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.genlcd_cntl3 = 0x000102aa,
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};
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static struct w100_gpio_regs corgi_fb_gpio = {
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.init_data1 = 0x000000bf,
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.init_data2 = 0x00000000,
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.gpio_dir1 = 0x00000000,
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.gpio_oe1 = 0x03c0feff,
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.gpio_dir2 = 0x00000000,
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.gpio_oe2 = 0x00000000,
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};
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static struct w100_mode corgi_fb_modes[] = {
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{
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.xres = 480,
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.yres = 640,
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.left_margin = 0x56,
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.right_margin = 0x55,
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.upper_margin = 0x03,
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.lower_margin = 0x00,
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.crtc_ss = 0x82360056,
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.crtc_ls = 0xA0280000,
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.crtc_gs = 0x80280028,
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.crtc_vpos_gs = 0x02830002,
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.crtc_rev = 0x00400008,
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.crtc_dclk = 0xA0000000,
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.crtc_gclk = 0x8015010F,
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.crtc_goe = 0x80100110,
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.crtc_ps1_active = 0x41060010,
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.pll_freq = 75,
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.fast_pll_freq = 100,
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.sysclk_src = CLK_SRC_PLL,
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.sysclk_divider = 0,
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.pixclk_src = CLK_SRC_PLL,
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.pixclk_divider = 2,
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.pixclk_divider_rotated = 6,
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},{
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.xres = 240,
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.yres = 320,
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.left_margin = 0x27,
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.right_margin = 0x2e,
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.upper_margin = 0x01,
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.lower_margin = 0x00,
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.crtc_ss = 0x81170027,
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.crtc_ls = 0xA0140000,
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.crtc_gs = 0xC0140014,
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.crtc_vpos_gs = 0x00010141,
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.crtc_rev = 0x00400008,
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.crtc_dclk = 0xA0000000,
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.crtc_gclk = 0x8015010F,
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.crtc_goe = 0x80100110,
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.crtc_ps1_active = 0x41060010,
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.pll_freq = 0,
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.fast_pll_freq = 0,
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.sysclk_src = CLK_SRC_XTAL,
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.sysclk_divider = 0,
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.pixclk_src = CLK_SRC_XTAL,
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.pixclk_divider = 1,
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.pixclk_divider_rotated = 1,
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},
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};
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static struct w100fb_mach_info corgi_fb_info = {
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.tg = &corgi_lcdtg_info,
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.init_mode = INIT_MODE_ROTATED,
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.mem = &corgi_fb_mem,
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.regs = &corgi_fb_regs,
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.modelist = &corgi_fb_modes[0],
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.num_modes = 2,
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.gpio = &corgi_fb_gpio,
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.xtal_freq = 12500000,
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.xtal_dbl = 0,
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};
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static struct resource corgi_fb_resources[] = {
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[0] = {
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.start = 0x08000000,
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.end = 0x08ffffff,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device corgifb_device = {
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.name = "w100fb",
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.id = -1,
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.num_resources = ARRAY_SIZE(corgi_fb_resources),
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.resource = corgi_fb_resources,
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.dev = {
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.platform_data = &corgi_fb_info,
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.parent = &corgissp_device.dev,
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},
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};
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