e6ed89ac9f
We don't enable the BTB on the ixp2350 as that can cause weird crashes (erratum #42.) However, some bootloaders enable the BTB, which means that we have to disable the BTB explicitly. Found thanks to Tom Rini. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
501 lines
13 KiB
ArmAsm
501 lines
13 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-xsc3.S
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*
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* Original Author: Matthew Gilbert
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* Current Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2004 (C) Intel Corp.
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is an
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* extension to Intel's original XScale core that adds the following
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* features:
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*
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* - ARMv6 Supersections
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* - Low Locality Reference pages (replaces mini-cache)
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* - 36-bit addressing
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* - L2 cache
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* - Cache-coherency if chipset supports it
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*
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* Based on orignal XScale code by Nicolas Pitre
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/procinfo.h>
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#include <asm/hardware.h>
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#include <asm/pgtable.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be flushed. If the
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* area is larger than this, then we flush the whole cache.
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*/
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#define MAX_AREA_SIZE 32768
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/*
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* The cache line size of the I and D cache.
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*/
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#define CACHELINESIZE 32
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/*
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* The size of the data cache.
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*/
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#define CACHESIZE 32768
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/*
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* Run with L2 enabled.
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*/
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#define L2_CACHE_ENABLE 1
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/*
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* Enable the Branch Target Buffer (can cause crashes, see erratum #42.)
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*/
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#define BTB_ENABLE 0
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/*
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* This macro is used to wait for a CP15 write and is needed
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* when we have to ensure that the last operation to the co-pro
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* was completed before continuing with operation.
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*/
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.macro cpwait_ret, lr, rd
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
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sub pc, \lr, \rd, LSR #32 @ wait for completion and
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@ flush instruction pipeline
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.endm
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/*
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* This macro cleans & invalidates the entire xsc3 dcache by set & way.
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*/
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.macro clean_d_cache rd, rs
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mov \rd, #0x1f00
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orr \rd, \rd, #0x00e0
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1: mcr p15, 0, \rd, c7, c14, 2 @ clean/inv set/way
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adds \rd, \rd, #0x40000000
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bcc 1b
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subs \rd, \rd, #0x20
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bpl 1b
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.endm
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.text
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/*
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* cpu_xsc3_proc_init()
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*
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* Nothing too exciting at the moment
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*/
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ENTRY(cpu_xsc3_proc_init)
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mov pc, lr
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/*
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* cpu_xsc3_proc_fin()
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*/
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ENTRY(cpu_xsc3_proc_fin)
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str lr, [sp, #-4]!
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mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r0
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bl xsc3_flush_kern_cache_all @ clean caches
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1800 @ ...IZ...........
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bic r0, r0, #0x0006 @ .............CA.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldr pc, [sp], #4
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/*
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* cpu_xsc3_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_xsc3_reset)
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r1 @ reset CPSR
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x0086 @ ........B....CA.
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bic r1, r1, #0x3900 @ ..VIZ..S........
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
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bic r1, r1, #0x0001 @ ...............M
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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@ CAUTION: MMU turned off from this point. We count on the pipeline
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@ already containing those two last instructions to survive.
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mov pc, r0
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/*
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* cpu_xsc3_do_idle()
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*
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* Cause the processor to idle
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*
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* For now we do nothing but go to idle mode for every case
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*
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* XScale supports clock switching, but using idle mode support
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* allows external hardware to react to system state changes.
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MMG: Come back to this one.
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*/
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.align 5
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ENTRY(cpu_xsc3_do_idle)
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mov r0, #1
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mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
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mov pc, lr
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/* ================================= CACHE ================================ */
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*/
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ENTRY(xsc3_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(xsc3_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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clean_d_cache r0, r1
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, vm_flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_area_struct describing address space
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*/
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.align 5
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ENTRY(xsc3_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #MAX_AREA_SIZE
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bhs __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
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mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate D cache line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* Note: single I-cache line invalidation isn't used here since
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* it also trashes the mini I-cache used by JTAG debuggers.
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*/
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ENTRY(xsc3_coherent_kern_range)
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/* FALLTHROUGH */
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ENTRY(xsc3_coherent_user_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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*/
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ENTRY(xsc3_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ Clean/Invalidate D Cache line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xsc3_dma_inv_range)
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tst r0, #CACHELINESIZE - 1
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bic r0, r0, #CACHELINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D entry
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mcrne p15, 1, r0, c7, c11, 1 @ clean L2 D entry
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tst r1, #CACHELINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D entry
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mcrne p15, 1, r1, c7, c11, 1 @ clean L2 D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D entry
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mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xsc3_dma_clean_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D entry
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mcr p15, 1, r0, c7, c11, 1 @ clean L2 D entry
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(xsc3_dma_flush_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate L1 D cache line
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mcr p15, 1, r0, c7, c11, 1 @ Clean L2 D cache line
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mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mov pc, lr
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ENTRY(xsc3_cache_fns)
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.long xsc3_flush_kern_cache_all
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.long xsc3_flush_user_cache_all
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.long xsc3_flush_user_cache_range
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.long xsc3_coherent_kern_range
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.long xsc3_coherent_user_range
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.long xsc3_flush_kern_dcache_page
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.long xsc3_dma_inv_range
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.long xsc3_dma_clean_range
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.long xsc3_dma_flush_range
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ENTRY(cpu_xsc3_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHELINESIZE
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subs r1, r1, #CACHELINESIZE
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bhi 1b
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mov pc, lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_xsc3_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 5
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ENTRY(cpu_xsc3_switch_mm)
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clean_d_cache r1, r2
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mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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#ifdef L2_CACHE_ENABLE
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orr r0, r0, #0x18 @ cache the page table in L2
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#endif
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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cpwait_ret lr, ip
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/*
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* cpu_xsc3_set_pte(ptep, pte)
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*
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* Set a PTE and flush it out
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*
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*/
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.align 5
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ENTRY(cpu_xsc3_set_pte)
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str r1, [r0], #-2048 @ linux version
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bic r2, r1, #0xdf0 @ Keep C, B, coherency bits
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orr r2, r2, #PTE_TYPE_EXT @ extended page
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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tst r3, #L_PTE_USER @ User?
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orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
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tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
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orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
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@ combined with user -> user r/w
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#if L2_CACHE_ENABLE
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@ If its cacheable it needs to be in L2 also.
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eor ip, r1, #L_PTE_CACHEABLE
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tst ip, #L_PTE_CACHEABLE
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orreq r2, r2, #PTE_EXT_TEX(0x5)
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#endif
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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movne r2, #0 @ no -> fault
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str r2, [r0] @ hardware version
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mov ip, #0
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mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line mcr
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mov pc, lr
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.ltorg
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.align
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__INIT
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.type __xsc3_setup, #function
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__xsc3_setup:
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mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
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#if L2_CACHE_ENABLE
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orr r4, r4, #0x18 @ cache the page table in L2
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#endif
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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mov r0, #1 @ Allow access to CP0 and CP13
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orr r0, r0, #1 << 13 @ Its undefined whether this
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mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
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mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
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and r0, r0, #2 @ preserve bit P bit setting
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#if L2_CACHE_ENABLE
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orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
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#endif
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mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
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mrc p15, 0, r0, c1, c0, 0 @ get control register
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bic r0, r0, #0x0002 @ .... .... .... ..A.
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orr r0, r0, #0x0005 @ .... .... .... .C.M
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#if BTB_ENABLE
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bic r0, r0, #0x0200 @ .... ..R. .... ....
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orr r0, r0, #0x3900 @ ..VI Z..S .... ....
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#else
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bic r0, r0, #0x0a00 @ .... Z.R. .... ....
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orr r0, r0, #0x3100 @ ..VI ...S .... ....
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#endif
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#if L2_CACHE_ENABLE
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orr r0, r0, #0x4000000 @ L2 enable
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#endif
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mov pc, lr
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.size __xsc3_setup, . - __xsc3_setup
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type xsc3_processor_functions, #object
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ENTRY(xsc3_processor_functions)
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.word v5t_early_abort
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.word cpu_xsc3_proc_init
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.word cpu_xsc3_proc_fin
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.word cpu_xsc3_reset
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.word cpu_xsc3_do_idle
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.word cpu_xsc3_dcache_clean_area
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.word cpu_xsc3_switch_mm
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.word cpu_xsc3_set_pte
|
|
.size xsc3_processor_functions, . - xsc3_processor_functions
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|
|
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.section ".rodata"
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|
|
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv5te"
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|
.size cpu_arch_name, . - cpu_arch_name
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|
|
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.type cpu_elf_name, #object
|
|
cpu_elf_name:
|
|
.asciz "v5"
|
|
.size cpu_elf_name, . - cpu_elf_name
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|
|
|
.type cpu_xsc3_name, #object
|
|
cpu_xsc3_name:
|
|
.asciz "XScale-Core3"
|
|
.size cpu_xsc3_name, . - cpu_xsc3_name
|
|
|
|
.align
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|
|
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.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
.type __xsc3_proc_info,#object
|
|
__xsc3_proc_info:
|
|
.long 0x69056000
|
|
.long 0xffffe000
|
|
.long 0x00000c0e
|
|
b __xsc3_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_xsc3_name
|
|
.long xsc3_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long xsc3_mc_user_fns
|
|
.long xsc3_cache_fns
|
|
.size __xsc3_proc_info, . - __xsc3_proc_info
|