465 lines
12 KiB
C
465 lines
12 KiB
C
/*
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* eisa.c - provide support for EISA adapters in PA-RISC machines
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
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* Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
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*
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* There are two distinct EISA adapters. Mongoose is found in machines
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* before the 712; then the Wax ASIC is used. To complicate matters, the
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* Wax ASIC also includes a PS/2 and RS-232 controller, but those are
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* dealt with elsewhere; this file is concerned only with the EISA portions
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* of Wax.
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*
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*
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* HINT:
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* -----
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* To allow an ISA card to work properly in the EISA slot you need to
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* set an edge trigger level. This may be done on the palo command line
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* by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
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* n and n2 as the irq levels you want to use.
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*
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* Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
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* irq levels 10 and 11.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/eisa.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/processor.h>
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#include <asm/parisc-device.h>
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#include <asm/delay.h>
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#include <asm/eisa_bus.h>
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#include <asm/eisa_eeprom.h>
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#if 0
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#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
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#else
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#define EISA_DBG(msg, arg... )
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#endif
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#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
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#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
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static DEFINE_SPINLOCK(eisa_irq_lock);
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void __iomem *eisa_eeprom_addr __read_mostly;
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/* We can only have one EISA adapter in the system because neither
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* implementation can be flexed.
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*/
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static struct eisa_ba {
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struct pci_hba_data hba;
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unsigned long eeprom_addr;
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struct eisa_root_device root;
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} eisa_dev;
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/* Port ops */
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static inline unsigned long eisa_permute(unsigned short port)
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{
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if (port & 0x300) {
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return 0xfc000000 | ((port & 0xfc00) >> 6)
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| ((port & 0x3f8) << 9) | (port & 7);
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} else {
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return 0xfc000000 | port;
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}
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}
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unsigned char eisa_in8(unsigned short port)
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{
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if (EISA_bus)
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return gsc_readb(eisa_permute(port));
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return 0xff;
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}
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unsigned short eisa_in16(unsigned short port)
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{
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if (EISA_bus)
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return le16_to_cpu(gsc_readw(eisa_permute(port)));
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return 0xffff;
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}
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unsigned int eisa_in32(unsigned short port)
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{
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if (EISA_bus)
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return le32_to_cpu(gsc_readl(eisa_permute(port)));
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return 0xffffffff;
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}
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void eisa_out8(unsigned char data, unsigned short port)
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{
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if (EISA_bus)
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gsc_writeb(data, eisa_permute(port));
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}
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void eisa_out16(unsigned short data, unsigned short port)
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{
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if (EISA_bus)
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gsc_writew(cpu_to_le16(data), eisa_permute(port));
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}
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void eisa_out32(unsigned int data, unsigned short port)
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{
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if (EISA_bus)
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gsc_writel(cpu_to_le32(data), eisa_permute(port));
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}
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#ifndef CONFIG_PCI
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/* We call these directly without PCI. See asm/io.h. */
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EXPORT_SYMBOL(eisa_in8);
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EXPORT_SYMBOL(eisa_in16);
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EXPORT_SYMBOL(eisa_in32);
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EXPORT_SYMBOL(eisa_out8);
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EXPORT_SYMBOL(eisa_out16);
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EXPORT_SYMBOL(eisa_out32);
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#endif
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/* Interrupt handling */
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/* cached interrupt mask registers */
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static int master_mask;
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static int slave_mask;
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/* the trig level can be set with the
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* eisa_irq_edge=n,n,n commandline parameter
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* We should really read this from the EEPROM
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* in the furure.
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*/
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/* irq 13,8,2,1,0 must be edge */
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static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
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/* called by free irq */
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static void eisa_disable_irq(unsigned int irq)
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{
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unsigned long flags;
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EISA_DBG("disable irq %d\n", irq);
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/* just mask for now */
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spin_lock_irqsave(&eisa_irq_lock, flags);
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if (irq & 8) {
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slave_mask |= (1 << (irq&7));
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eisa_out8(slave_mask, 0xa1);
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} else {
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master_mask |= (1 << (irq&7));
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eisa_out8(master_mask, 0x21);
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}
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
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EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
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}
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/* called by request irq */
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static void eisa_enable_irq(unsigned int irq)
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{
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unsigned long flags;
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EISA_DBG("enable irq %d\n", irq);
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spin_lock_irqsave(&eisa_irq_lock, flags);
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if (irq & 8) {
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slave_mask &= ~(1 << (irq&7));
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eisa_out8(slave_mask, 0xa1);
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} else {
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master_mask &= ~(1 << (irq&7));
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eisa_out8(master_mask, 0x21);
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}
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
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EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
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}
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static unsigned int eisa_startup_irq(unsigned int irq)
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{
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eisa_enable_irq(irq);
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return 0;
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}
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static struct hw_interrupt_type eisa_interrupt_type = {
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.typename = "EISA",
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.startup = eisa_startup_irq,
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.shutdown = eisa_disable_irq,
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.enable = eisa_enable_irq,
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.disable = eisa_disable_irq,
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.ack = no_ack_irq,
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.end = no_end_irq,
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};
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static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
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{
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int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
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unsigned long flags;
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spin_lock_irqsave(&eisa_irq_lock, flags);
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/* read IRR command */
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eisa_out8(0x0a, 0x20);
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eisa_out8(0x0a, 0xa0);
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EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
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irq, eisa_in8(0x20), eisa_in8(0xa0));
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/* read ISR command */
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eisa_out8(0x0a, 0x20);
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eisa_out8(0x0a, 0xa0);
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EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
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eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
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irq &= 0xf;
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/* mask irq and write eoi */
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if (irq & 8) {
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slave_mask |= (1 << (irq&7));
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eisa_out8(slave_mask, 0xa1);
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eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
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eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
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} else {
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master_mask |= (1 << (irq&7));
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eisa_out8(master_mask, 0x21);
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eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */
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}
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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__do_IRQ(irq, regs);
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spin_lock_irqsave(&eisa_irq_lock, flags);
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/* unmask */
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if (irq & 8) {
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slave_mask &= ~(1 << (irq&7));
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eisa_out8(slave_mask, 0xa1);
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} else {
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master_mask &= ~(1 << (irq&7));
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eisa_out8(master_mask, 0x21);
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}
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t dummy_irq2_handler(int _, void *dev)
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{
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printk(KERN_ALERT "eisa: uhh, irq2?\n");
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return IRQ_HANDLED;
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}
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static struct irqaction irq2_action = {
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.handler = dummy_irq2_handler,
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.name = "cascade",
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};
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static void init_eisa_pic(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&eisa_irq_lock, flags);
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eisa_out8(0xff, 0x21); /* mask during init */
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eisa_out8(0xff, 0xa1); /* mask during init */
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/* master pic */
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eisa_out8(0x11,0x20); /* ICW1 */
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eisa_out8(0x00,0x21); /* ICW2 */
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eisa_out8(0x04,0x21); /* ICW3 */
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eisa_out8(0x01,0x21); /* ICW4 */
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eisa_out8(0x40,0x20); /* OCW2 */
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/* slave pic */
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eisa_out8(0x11,0xa0); /* ICW1 */
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eisa_out8(0x08,0xa1); /* ICW2 */
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eisa_out8(0x02,0xa1); /* ICW3 */
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eisa_out8(0x01,0xa1); /* ICW4 */
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eisa_out8(0x40,0xa0); /* OCW2 */
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udelay(100);
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slave_mask = 0xff;
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master_mask = 0xfb;
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eisa_out8(slave_mask, 0xa1); /* OCW1 */
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eisa_out8(master_mask, 0x21); /* OCW1 */
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/* setup trig level */
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EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
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eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
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eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
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EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
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EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
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EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
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EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
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spin_unlock_irqrestore(&eisa_irq_lock, flags);
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}
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/* Device initialisation */
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#define is_mongoose(dev) (dev->id.sversion == 0x00076)
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static int __devinit eisa_probe(struct parisc_device *dev)
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{
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int i, result;
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char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
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printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
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name, dev->hpa.start);
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eisa_dev.hba.dev = dev;
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eisa_dev.hba.iommu = ccio_get_iommu(dev);
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eisa_dev.hba.lmmio_space.name = "EISA";
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eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
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eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
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eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
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result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
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if (result < 0) {
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printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
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return result;
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}
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eisa_dev.hba.io_space.name = "EISA";
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eisa_dev.hba.io_space.start = 0;
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eisa_dev.hba.io_space.end = 0xffff;
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eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
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result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
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if (result < 0) {
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printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
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return result;
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}
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pcibios_register_hba(&eisa_dev.hba);
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result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
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if (result) {
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printk(KERN_ERR "EISA: request_irq failed!\n");
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return result;
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}
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/* Reserve IRQ2 */
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irq_desc[2].action = &irq2_action;
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for (i = 0; i < 16; i++) {
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irq_desc[i].chip = &eisa_interrupt_type;
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}
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EISA_bus = 1;
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if (dev->num_addrs) {
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/* newer firmware hand out the eeprom address */
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eisa_dev.eeprom_addr = dev->addr[0];
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} else {
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/* old firmware, need to figure out the box */
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if (is_mongoose(dev)) {
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eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
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} else {
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eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
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}
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}
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eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
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result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
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&eisa_dev.hba.lmmio_space);
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init_eisa_pic();
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if (result >= 0) {
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/* FIXME : Don't enumerate the bus twice. */
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eisa_dev.root.dev = &dev->dev;
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dev->dev.driver_data = &eisa_dev.root;
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eisa_dev.root.bus_base_addr = 0;
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eisa_dev.root.res = &eisa_dev.hba.io_space;
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eisa_dev.root.slots = result;
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eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
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if (eisa_root_register (&eisa_dev.root)) {
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printk(KERN_ERR "EISA: Failed to register EISA root\n");
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return -1;
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}
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}
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return 0;
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}
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static struct parisc_device_id eisa_tbl[] = {
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{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
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{ HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
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{ 0, }
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};
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MODULE_DEVICE_TABLE(parisc, eisa_tbl);
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static struct parisc_driver eisa_driver = {
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.name = "eisa_ba",
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.id_table = eisa_tbl,
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.probe = eisa_probe,
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};
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void __init eisa_init(void)
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{
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register_parisc_driver(&eisa_driver);
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}
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static unsigned int eisa_irq_configured;
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void eisa_make_irq_level(int num)
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{
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if (eisa_irq_configured& (1<<num)) {
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printk(KERN_WARNING
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"IRQ %d polarity configured twice (last to level)\n",
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num);
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}
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eisa_irq_level |= (1<<num); /* set the corresponding bit */
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eisa_irq_configured |= (1<<num); /* set the corresponding bit */
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}
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void eisa_make_irq_edge(int num)
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{
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if (eisa_irq_configured& (1<<num)) {
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printk(KERN_WARNING
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"IRQ %d polarity configured twice (last to edge)\n",
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num);
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}
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eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
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eisa_irq_configured |= (1<<num); /* set the corresponding bit */
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}
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static int __init eisa_irq_setup(char *str)
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{
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char *cur = str;
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int val;
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EISA_DBG("IRQ setup\n");
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while (cur != NULL) {
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char *pe;
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val = (int) simple_strtoul(cur, &pe, 0);
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if (val > 15 || val < 0) {
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printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
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continue;
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}
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if (val == 2) {
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val = 9;
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}
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eisa_make_irq_edge(val); /* clear the corresponding bit */
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EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
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if ((cur = strchr(cur, ','))) {
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cur++;
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} else {
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break;
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}
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}
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return 1;
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}
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__setup("eisa_irq_edge=", eisa_irq_setup);
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