208 lines
3.4 KiB
ArmAsm
208 lines
3.4 KiB
ArmAsm
/*
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* Common Blackfin startup code
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*
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/blackfin.h>
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#include <asm/thread_info.h>
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#include <asm/trace.h>
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__INIT
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#define INITIAL_STACK (L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
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ENTRY(__start)
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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/* Enable Cycle Counter and Nesting Of Interrupts */
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#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
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R0 = SYSCFG_SNEN;
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#else
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R0 = SYSCFG_SNEN | SYSCFG_CCEN;
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#endif
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SYSCFG = R0;
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R0 = 0;
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/* Clear Out All the data and pointer Registers */
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R1 = R0;
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R2 = R0;
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R3 = R0;
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R4 = R0;
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R5 = R0;
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R6 = R0;
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P0 = R0;
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P1 = R0;
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P2 = R0;
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P3 = R0;
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P4 = R0;
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P5 = R0;
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LC0 = r0;
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LC1 = r0;
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L0 = r0;
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L1 = r0;
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers */
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B0 = r0;
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B1 = r0;
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B2 = r0;
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B3 = r0;
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I0 = r0;
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I1 = r0;
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I2 = r0;
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I3 = r0;
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M0 = r0;
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M1 = r0;
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M2 = r0;
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M3 = r0;
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trace_buffer_init(p0,r0);
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P0 = R1;
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R0 = R1;
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/* Turn off the icache */
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p0.l = LO(IMEM_CONTROL);
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p0.h = HI(IMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENICPLB;
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R0 = R0 & R1;
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[p0] = R0;
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SSYNC;
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/* Turn off the dcache */
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p0.l = LO(DMEM_CONTROL);
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p0.h = HI(DMEM_CONTROL);
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R1 = [p0];
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R0 = ~ENDCPLB;
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R0 = R0 & R1;
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[p0] = R0;
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SSYNC;
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/* Save RETX, in case of doublefault */
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p0.l = ___retx;
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p0.h = ___retx;
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R0 = RETX;
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[P0] = R0;
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/* Initialize stack pointer */
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sp.l = lo(INITIAL_STACK);
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sp.h = hi(INITIAL_STACK);
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fp = sp;
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usp = sp;
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#ifdef CONFIG_EARLY_PRINTK
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call _init_early_exception_vectors;
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#endif
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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/* This section keeps the processor in supervisor mode
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* during kernel boot. Switches to user mode at end of boot.
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* See page 3-9 of Hardware Reference manual for documentation.
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*/
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/* EVT15 = _real_start */
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p0.l = lo(EVT15);
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p0.h = hi(EVT15);
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p1.l = _real_start;
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p1.h = _real_start;
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[p0] = p1;
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csync;
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p0.l = lo(IMASK);
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p0.h = hi(IMASK);
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p1.l = IMASK_IVG15;
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p1.h = 0x0;
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[p0] = p1;
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csync;
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raise 15;
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p0.l = .LWAIT_HERE;
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p0.h = .LWAIT_HERE;
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reti = p0;
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#if ANOMALY_05000281
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nop; nop; nop;
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#endif
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rti;
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.LWAIT_HERE:
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jump .LWAIT_HERE;
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ENDPROC(__start)
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/* A little BF561 glue ... */
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#ifndef WDOG_CTL
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# define WDOG_CTL WDOGA_CTL
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#endif
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ENTRY(_real_start)
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/* Enable nested interrupts */
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[--sp] = reti;
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/* watchdog off for now */
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p0.l = lo(WDOG_CTL);
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p0.h = hi(WDOG_CTL);
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r0 = 0xAD6(z);
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w[p0] = r0;
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ssync;
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/* Zero out the bss region
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* Note: this will fail if bss is 0 bytes ...
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*/
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r0 = 0 (z);
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r1.l = ___bss_start;
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r1.h = ___bss_start;
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r2.l = ___bss_stop;
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r2.h = ___bss_stop;
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r2 = r2 - r1;
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r2 >>= 2;
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p1 = r1;
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p2 = r2;
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lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
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.L_clear_bss:
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[p1++] = r0;
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/* In case there is a NULL pointer reference,
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* zero out region before stext
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*/
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p1 = r0;
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r2.l = __stext;
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r2.h = __stext;
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r2 >>= 2;
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p2 = r2;
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lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
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.L_clear_zero:
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[p1++] = r0;
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/* Pass the u-boot arguments to the global value command line */
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R0 = R7;
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call _cmdline_init;
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/* Load the current thread pointer and stack */
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sp.l = _init_thread_union;
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sp.h = _init_thread_union;
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p1 = THREAD_SIZE (z);
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sp = sp + p1;
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usp = sp;
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fp = sp;
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jump.l _start_kernel;
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ENDPROC(_real_start)
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__FINIT
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