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Kim Phillips d8a6a443ff perf/x86/amd: Constrain Large Increment per Cycle events 
[ Upstream commit 471af006a7 ]

AMD Family 17h processors and above gain support for Large Increment
per Cycle events.  Unfortunately there is no CPUID or equivalent bit
that indicates whether the feature exists or not, so we continue to
determine eligibility based on a CPU family number comparison.

For Large Increment per Cycle events, we add a f17h-and-compatibles
get_event_constraints_f17h() that returns an even counter bitmask:
Large Increment per Cycle events can only be placed on PMCs 0, 2,
and 4 out of the currently available 0-5.  The only currently
public event that requires this feature to report valid counts
is PMCx003 "Retired SSE/AVX Operations".

Note that the CPU family logic in amd_core_pmu_init() is changed
so as to be able to selectively add initialization for features
available in ranges of backward-compatible CPU families.  This
Large Increment per Cycle feature is expected to be retained
in future families.

A side-effect of assigning a new get_constraints function for f17h
disables calling the old (prior to f15h) amd_get_event_constraints
implementation left enabled by commit e40ed1542d ("perf/x86: Add perf
support for AMD family-17h processors"), which is no longer
necessary since those North Bridge event codes are obsoleted.

Also fix a spelling mistake whilst in the area (calulating ->
calculating).

Fixes: e40ed1542d ("perf/x86: Add perf support for AMD family-17h processors")
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20191114183720.19887-2-kim.phillips@amd.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
 		2020-02-24 08:36:52 +01:00
..
amd perf/x86/amd: Constrain Large Increment per Cycle events 2020-02-24 08:36:52 +01:00
intel perf/x86/intel: Fix inaccurate period in context switch for auto-reload 2020-02-19 19:53:07 +01:00
Kconfig
…
Makefile perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
core.c perf/x86/intel: Fix PT PMI handling 2020-01-12 12:21:36 +01:00
msr.c perf/x86/msr: Add Tiger Lake CPU support 2019-10-12 15:13:09 +02:00
perf_event.h perf/x86/amd: Constrain Large Increment per Cycle events 2020-02-24 08:36:52 +01:00
probe.c perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00
probe.h perf/x86: Add MSR probe interface 2019-06-24 19:28:31 +02:00