ea5a9607cb
As part of the gpio driver consolidation, this patch moves the Tegra driver into drivers/gpio Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Colin Cross <ccross@android.com>
432 lines
10 KiB
C
432 lines
10 KiB
C
/*
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* arch/arm/mach-tegra/gpio.c
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*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <asm/mach/irq.h>
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#include <mach/iomap.h>
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#include <mach/suspend.h>
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_PORT(x) (((x) >> 3) & 0x3)
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#define GPIO_BIT(x) ((x) & 0x7)
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#define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \
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GPIO_BANK(x) * 0x80 + \
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GPIO_PORT(x) * 4)
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#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
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#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
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#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
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#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
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#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
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#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
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#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
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#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
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#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
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#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
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#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
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#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
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#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
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#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
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#define GPIO_INT_LVL_MASK 0x010101
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#define GPIO_INT_LVL_EDGE_RISING 0x000101
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#define GPIO_INT_LVL_EDGE_FALLING 0x000100
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#define GPIO_INT_LVL_EDGE_BOTH 0x010100
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#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
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#define GPIO_INT_LVL_LEVEL_LOW 0x000000
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struct tegra_gpio_bank {
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int bank;
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int irq;
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spinlock_t lvl_lock[4];
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#ifdef CONFIG_PM
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u32 cnf[4];
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u32 out[4];
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u32 oe[4];
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u32 int_enb[4];
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u32 int_lvl[4];
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#endif
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};
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static struct tegra_gpio_bank tegra_gpio_banks[] = {
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{.bank = 0, .irq = INT_GPIO1},
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{.bank = 1, .irq = INT_GPIO2},
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{.bank = 2, .irq = INT_GPIO3},
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{.bank = 3, .irq = INT_GPIO4},
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{.bank = 4, .irq = INT_GPIO5},
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{.bank = 5, .irq = INT_GPIO6},
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{.bank = 6, .irq = INT_GPIO7},
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};
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static int tegra_gpio_compose(int bank, int port, int bit)
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{
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return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
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}
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static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
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{
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u32 val;
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val = 0x100 << GPIO_BIT(gpio);
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if (value)
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val |= 1 << GPIO_BIT(gpio);
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__raw_writel(val, reg);
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}
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void tegra_gpio_enable(int gpio)
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{
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tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
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}
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void tegra_gpio_disable(int gpio)
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{
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tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
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}
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static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
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}
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static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
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}
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static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
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return 0;
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}
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static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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tegra_gpio_set(chip, offset, value);
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tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
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return 0;
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}
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static struct gpio_chip tegra_gpio_chip = {
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.label = "tegra-gpio",
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.direction_input = tegra_gpio_direction_input,
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.get = tegra_gpio_get,
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.direction_output = tegra_gpio_direction_output,
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.set = tegra_gpio_set,
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.base = 0,
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.ngpio = TEGRA_NR_GPIOS,
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};
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static void tegra_gpio_irq_ack(struct irq_data *d)
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{
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int gpio = d->irq - INT_GPIO_BASE;
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__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
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}
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static void tegra_gpio_irq_mask(struct irq_data *d)
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{
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int gpio = d->irq - INT_GPIO_BASE;
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tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
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}
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static void tegra_gpio_irq_unmask(struct irq_data *d)
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{
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int gpio = d->irq - INT_GPIO_BASE;
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tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
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}
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static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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int gpio = d->irq - INT_GPIO_BASE;
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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int port = GPIO_PORT(gpio);
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int lvl_type;
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int val;
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unsigned long flags;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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lvl_type = GPIO_INT_LVL_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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lvl_type = GPIO_INT_LVL_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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lvl_type = GPIO_INT_LVL_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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lvl_type = GPIO_INT_LVL_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->lvl_lock[port], flags);
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val = __raw_readl(GPIO_INT_LVL(gpio));
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val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
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val |= lvl_type << GPIO_BIT(gpio);
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__raw_writel(val, GPIO_INT_LVL(gpio));
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spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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return 0;
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}
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static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct tegra_gpio_bank *bank;
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int port;
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int pin;
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int unmasked = 0;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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bank = irq_get_handler_data(irq);
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for (port = 0; port < 4; port++) {
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int gpio = tegra_gpio_compose(bank->bank, port, 0);
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unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
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__raw_readl(GPIO_INT_ENB(gpio));
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u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
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for_each_set_bit(pin, &sta, 8) {
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__raw_writel(1 << pin, GPIO_INT_CLR(gpio));
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/* if gpio is edge triggered, clear condition
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* before executing the hander so that we don't
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* miss edges
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*/
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if (lvl & (0x100 << pin)) {
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unmasked = 1;
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chained_irq_exit(chip, desc);
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}
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generic_handle_irq(gpio_to_irq(gpio + pin));
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}
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}
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if (!unmasked)
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chained_irq_exit(chip, desc);
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}
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#ifdef CONFIG_PM
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void tegra_gpio_resume(void)
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{
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unsigned long flags;
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int b;
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int p;
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local_irq_save(flags);
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for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
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struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
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for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
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unsigned int gpio = (b<<5) | (p<<3);
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__raw_writel(bank->cnf[p], GPIO_CNF(gpio));
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__raw_writel(bank->out[p], GPIO_OUT(gpio));
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__raw_writel(bank->oe[p], GPIO_OE(gpio));
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__raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
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__raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
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}
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}
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local_irq_restore(flags);
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}
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void tegra_gpio_suspend(void)
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{
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unsigned long flags;
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int b;
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int p;
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local_irq_save(flags);
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for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
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struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
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for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
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unsigned int gpio = (b<<5) | (p<<3);
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bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
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bank->out[p] = __raw_readl(GPIO_OUT(gpio));
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bank->oe[p] = __raw_readl(GPIO_OE(gpio));
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bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
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bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
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}
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}
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local_irq_restore(flags);
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}
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static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
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{
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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return irq_set_irq_wake(bank->irq, enable);
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}
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#endif
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static struct irq_chip tegra_gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = tegra_gpio_irq_ack,
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.irq_mask = tegra_gpio_irq_mask,
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.irq_unmask = tegra_gpio_irq_unmask,
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.irq_set_type = tegra_gpio_irq_set_type,
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#ifdef CONFIG_PM
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.irq_set_wake = tegra_gpio_wake_enable,
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#endif
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};
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/* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key gpio_lock_class;
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static int __init tegra_gpio_init(void)
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{
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struct tegra_gpio_bank *bank;
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int i;
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int j;
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for (i = 0; i < 7; i++) {
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for (j = 0; j < 4; j++) {
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int gpio = tegra_gpio_compose(i, j, 0);
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__raw_writel(0x00, GPIO_INT_ENB(gpio));
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}
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}
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gpiochip_add(&tegra_gpio_chip);
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for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
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bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
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irq_set_lockdep_class(i, &gpio_lock_class);
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irq_set_chip_data(i, bank);
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irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
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handle_simple_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
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bank = &tegra_gpio_banks[i];
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irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
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irq_set_handler_data(bank->irq, bank);
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for (j = 0; j < 4; j++)
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spin_lock_init(&bank->lvl_lock[j]);
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}
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return 0;
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}
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postcore_initcall(tegra_gpio_init);
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void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
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{
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int i;
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for (i = 0; i < num; i++) {
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int gpio = table[i].gpio;
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if (table[i].enable)
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tegra_gpio_enable(gpio);
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else
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tegra_gpio_disable(gpio);
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}
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}
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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static int dbg_gpio_show(struct seq_file *s, void *unused)
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{
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int i;
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int j;
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for (i = 0; i < 7; i++) {
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for (j = 0; j < 4; j++) {
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int gpio = tegra_gpio_compose(i, j, 0);
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seq_printf(s,
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"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
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i, j,
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__raw_readl(GPIO_CNF(gpio)),
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__raw_readl(GPIO_OE(gpio)),
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__raw_readl(GPIO_OUT(gpio)),
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__raw_readl(GPIO_IN(gpio)),
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__raw_readl(GPIO_INT_STA(gpio)),
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__raw_readl(GPIO_INT_ENB(gpio)),
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__raw_readl(GPIO_INT_LVL(gpio)));
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}
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}
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return 0;
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}
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static int dbg_gpio_open(struct inode *inode, struct file *file)
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{
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return single_open(file, dbg_gpio_show, &inode->i_private);
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}
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static const struct file_operations debug_fops = {
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.open = dbg_gpio_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init tegra_gpio_debuginit(void)
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{
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(void) debugfs_create_file("tegra_gpio", S_IRUGO,
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NULL, NULL, &debug_fops);
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return 0;
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}
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late_initcall(tegra_gpio_debuginit);
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#endif
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