f151749440
Initial register bank cleanup. Make SR.RB configurable, and add some preliminary documentation on register bank usage within the kernel. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
360 lines
8.7 KiB
C
360 lines
8.7 KiB
C
#ifndef __ASM_SH_SYSTEM_H
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#define __ASM_SH_SYSTEM_H
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/*
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
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* Copyright (C) 2002 Paul Mundt
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*/
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#include <asm/types.h>
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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#define switch_to(prev, next, last) do { \
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struct task_struct *__last; \
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register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
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register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
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register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
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register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
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register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
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register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
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__asm__ __volatile__ (".balign 4\n\t" \
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"stc.l gbr, @-r15\n\t" \
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"sts.l pr, @-r15\n\t" \
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"mov.l r8, @-r15\n\t" \
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"mov.l r9, @-r15\n\t" \
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"mov.l r10, @-r15\n\t" \
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"mov.l r11, @-r15\n\t" \
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"mov.l r12, @-r15\n\t" \
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"mov.l r13, @-r15\n\t" \
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"mov.l r14, @-r15\n\t" \
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"mov.l r15, @r1 ! save SP\n\t" \
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"mov.l @r6, r15 ! change to new stack\n\t" \
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"mova 1f, %0\n\t" \
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"mov.l %0, @r2 ! save PC\n\t" \
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"mov.l 2f, %0\n\t" \
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"jmp @%0 ! call __switch_to\n\t" \
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" lds r7, pr ! with return to new PC\n\t" \
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".balign 4\n" \
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"2:\n\t" \
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".long __switch_to\n" \
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"1:\n\t" \
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"mov.l @r15+, r14\n\t" \
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"mov.l @r15+, r13\n\t" \
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"mov.l @r15+, r12\n\t" \
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"mov.l @r15+, r11\n\t" \
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"mov.l @r15+, r10\n\t" \
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"mov.l @r15+, r9\n\t" \
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"mov.l @r15+, r8\n\t" \
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"lds.l @r15+, pr\n\t" \
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"ldc.l @r15+, gbr\n\t" \
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: "=z" (__last) \
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: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
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"r" (__ts5), "r" (__ts6), "r" (__ts7) \
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: "r3", "t"); \
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last = __last; \
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} while (0)
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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#ifdef CONFIG_CPU_SH4A
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#define __icbi() \
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{ \
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unsigned long __addr; \
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__addr = 0xa8000000; \
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__asm__ __volatile__( \
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"icbi %0\n\t" \
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: /* no output */ \
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: "m" (__m(__addr))); \
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}
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#endif
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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static __inline__ unsigned long tas(volatile int *m)
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{ /* #define tas(ptr) (xchg((ptr),1)) */
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unsigned long retval;
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__asm__ __volatile__ ("tas.b @%1\n\t"
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"movt %0"
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: "=r" (retval): "r" (m): "t", "memory");
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return retval;
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}
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extern void __xchg_called_with_bad_pointer(void);
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/*
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* A brief note on ctrl_barrier(), the control register write barrier.
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*
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* Legacy SH cores typically require a sequence of 8 nops after
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* modification of a control register in order for the changes to take
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* effect. On newer cores (like the sh4a and sh5) this is accomplished
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* with icbi.
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*
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* Also note that on sh4a in the icbi case we can forego a synco for the
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* write barrier, as it's not necessary for control registers.
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*
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* Historically we have only done this type of barrier for the MMUCR, but
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* it's also necessary for the CCR, so we make it generic here instead.
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*/
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#ifdef CONFIG_CPU_SH4A
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("synco": : :"memory")
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#define ctrl_barrier() __icbi()
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#define read_barrier_depends() do { } while(0)
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#else
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#define mb() __asm__ __volatile__ ("": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
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#define read_barrier_depends() do { } while(0)
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#endif
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#define set_mb(var, value) do { xchg(&var, value); } while (0)
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/* Interrupt Control */
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#ifdef CONFIG_CPU_HAS_SR_RB
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static inline void local_irq_enable(void)
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{
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unsigned long __dummy0, __dummy1;
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__asm__ __volatile__("stc sr, %0\n\t"
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"and %1, %0\n\t"
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"stc r6_bank, %1\n\t"
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"or %1, %0\n\t"
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"ldc %0, sr"
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: "=&r" (__dummy0), "=r" (__dummy1)
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: "1" (~0x000000f0)
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: "memory");
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}
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#else
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static inline void local_irq_enable(void)
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{
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unsigned long __dummy0, __dummy1;
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__asm__ __volatile__ (
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"stc sr, %0\n\t"
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"and %1, %0\n\t"
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"ldc %0, sr\n\t"
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: "=&r" (__dummy0), "=r" (__dummy1)
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: "1" (~0x000000f0)
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: "memory");
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}
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#endif
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static __inline__ void local_irq_disable(void)
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{
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unsigned long __dummy;
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__asm__ __volatile__("stc sr, %0\n\t"
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"or #0xf0, %0\n\t"
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"ldc %0, sr"
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: "=&z" (__dummy)
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: /* no inputs */
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: "memory");
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}
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#define local_save_flags(x) \
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__asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
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#define irqs_disabled() \
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({ \
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unsigned long flags; \
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local_save_flags(flags); \
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(flags != 0); \
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})
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static __inline__ unsigned long local_irq_save(void)
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{
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unsigned long flags, __dummy;
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__asm__ __volatile__("stc sr, %1\n\t"
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"mov %1, %0\n\t"
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"or #0xf0, %0\n\t"
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"ldc %0, sr\n\t"
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"mov %1, %0\n\t"
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"and #0xf0, %0"
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: "=&z" (flags), "=&r" (__dummy)
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:/**/
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: "memory" );
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return flags;
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}
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#ifdef DEBUG_CLI_STI
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static __inline__ void local_irq_restore(unsigned long x)
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{
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if ((x & 0x000000f0) != 0x000000f0)
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local_irq_enable();
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else {
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unsigned long flags;
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local_save_flags(flags);
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if (flags == 0) {
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extern void dump_stack(void);
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printk(KERN_ERR "BUG!\n");
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dump_stack();
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local_irq_disable();
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}
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}
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}
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#else
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#define local_irq_restore(x) do { \
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if ((x & 0x000000f0) != 0x000000f0) \
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local_irq_enable(); \
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} while (0)
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#endif
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#define really_restore_flags(x) do { \
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if ((x & 0x000000f0) != 0x000000f0) \
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local_irq_enable(); \
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else \
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local_irq_disable(); \
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} while (0)
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/*
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* Jump to P2 area.
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* When handling TLB or caches, we need to do it from P2 area.
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*/
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#define jump_to_P2() \
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do { \
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unsigned long __dummy; \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"or %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy) \
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: "r" (0x20000000)); \
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} while (0)
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/*
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* Back to P1 area.
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*/
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#define back_to_P1() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0)
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/* For spinlocks etc */
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#define local_irq_save(x) x = local_irq_save()
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static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
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{
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unsigned long flags, retval;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags);
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return retval;
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}
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static __inline__ unsigned long xchg_u8(volatile unsigned char * m, unsigned long val)
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{
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unsigned long flags, retval;
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local_irq_save(flags);
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retval = *m;
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*m = val & 0xff;
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local_irq_restore(flags);
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return retval;
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}
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static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return xchg_u32(ptr, x);
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break;
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case 1:
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return xchg_u8(ptr, x);
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break;
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
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unsigned long new)
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{
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__u32 retval;
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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if (retval == old)
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*m = new;
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local_irq_restore(flags); /* implies memory barrier */
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return retval;
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}
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/* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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/* XXX
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* disable hlt during certain critical i/o operations
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*/
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#define HAVE_DISABLE_HLT
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void disable_hlt(void);
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void enable_hlt(void);
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#define arch_align_stack(x) (x)
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#endif
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