f187616b36
Legacy clock data is initialialized slightly differently compared to DT clocks, thus add support for this. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
167 lines
3.3 KiB
C
167 lines
3.3 KiB
C
/*
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* TI Clock driver internal definitions
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*
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* Copyright (C) 2014 Texas Instruments, Inc
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* Tero Kristo (t-kristo@ti.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_CLK_TI_CLOCK__
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#define __DRIVERS_CLK_TI_CLOCK__
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enum {
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TI_CLK_FIXED,
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TI_CLK_MUX,
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TI_CLK_DIVIDER,
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TI_CLK_COMPOSITE,
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TI_CLK_FIXED_FACTOR,
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TI_CLK_GATE,
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TI_CLK_DPLL,
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};
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/* Global flags */
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#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
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#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
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#define CLKF_SET_RATE_PARENT (1 << 2)
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#define CLKF_OMAP3 (1 << 3)
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#define CLKF_AM35XX (1 << 4)
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/* Gate flags */
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#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
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#define CLKF_INTERFACE (1 << 6)
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#define CLKF_SSI (1 << 7)
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#define CLKF_DSS (1 << 8)
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#define CLKF_HSOTGUSB (1 << 9)
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#define CLKF_WAIT (1 << 10)
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#define CLKF_NO_WAIT (1 << 11)
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#define CLKF_HSDIV (1 << 12)
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#define CLKF_CLKDM (1 << 13)
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/* DPLL flags */
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#define CLKF_LOW_POWER_STOP (1 << 5)
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#define CLKF_LOCK (1 << 6)
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#define CLKF_LOW_POWER_BYPASS (1 << 7)
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#define CLKF_PER (1 << 8)
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#define CLKF_CORE (1 << 9)
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#define CLKF_J_TYPE (1 << 10)
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#define CLK(dev, con, ck) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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}, \
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.clk = ck, \
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}
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struct ti_clk {
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const char *name;
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const char *clkdm_name;
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int type;
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void *data;
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struct ti_clk *patch;
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struct clk *clk;
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};
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struct ti_clk_alias {
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struct ti_clk *clk;
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struct clk_lookup lk;
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struct list_head link;
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};
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struct ti_clk_fixed {
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u32 frequency;
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u16 flags;
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};
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struct ti_clk_mux {
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u8 bit_shift;
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int num_parents;
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u16 reg;
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u8 module;
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const char **parents;
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u16 flags;
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};
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struct ti_clk_divider {
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const char *parent;
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u8 bit_shift;
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u16 max_div;
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u16 reg;
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u8 module;
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int *dividers;
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int num_dividers;
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u16 flags;
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};
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struct ti_clk_fixed_factor {
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const char *parent;
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u16 div;
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u16 mult;
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u16 flags;
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};
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struct ti_clk_gate {
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const char *parent;
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u8 bit_shift;
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u16 reg;
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u8 module;
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u16 flags;
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};
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struct ti_clk_composite {
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struct ti_clk_divider *divider;
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struct ti_clk_mux *mux;
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struct ti_clk_gate *gate;
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u16 flags;
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};
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struct ti_clk_clkdm_gate {
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const char *parent;
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u16 flags;
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};
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struct ti_clk_dpll {
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int num_parents;
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u16 control_reg;
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u16 idlest_reg;
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u16 autoidle_reg;
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u16 mult_div1_reg;
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u8 module;
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const char **parents;
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u16 flags;
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u8 modes;
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u32 mult_mask;
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u32 div1_mask;
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u32 enable_mask;
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u32 autoidle_mask;
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u32 freqsel_mask;
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u32 idlest_mask;
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u32 dco_mask;
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u32 sddiv_mask;
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u16 max_multiplier;
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u16 max_divider;
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u8 auto_recal_bit;
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u8 recal_en_bit;
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u8 recal_st_bit;
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};
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struct clk *ti_clk_register_gate(struct ti_clk *setup);
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struct clk *ti_clk_register_mux(struct ti_clk *setup);
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struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
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struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
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void ti_clk_patch_legacy_clks(struct ti_clk **patch);
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struct clk *ti_clk_register_clk(struct ti_clk *setup);
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int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
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#endif
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