5dfa9c1b4f
This patch updates NEC VR4100 series CPU-PCI bridge support. Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
127 lines
3.2 KiB
C
127 lines
3.2 KiB
C
/*
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* ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
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*
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* Copyright (C) 2001-2003 MontaVista Software Inc.
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* Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
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* Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Changes:
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* MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
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* - New creation, NEC VR4122 and VR4131 are supported.
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*/
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14)
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#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
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static inline int set_pci_configuration_address(unsigned char number,
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unsigned int devfn, int where)
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{
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if (number == 0) {
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/*
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* Type 0 configuration
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*/
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if (PCI_SLOT(devfn) < 11 || where > 0xff)
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return -EINVAL;
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writel((1U << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
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(where & 0xfc), PCICONFAREG);
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} else {
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/*
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* Type 1 configuration
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*/
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if (where > 0xff)
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return -EINVAL;
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writel(((uint32_t)number << 16) | ((devfn & 0xff) << 8) |
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(where & 0xfc) | 1U, PCICONFAREG);
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}
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return 0;
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *val)
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{
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uint32_t data;
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*val = 0xffffffffU;
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if (set_pci_configuration_address(bus->number, devfn, where) < 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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data = readl(PCICONFDREG);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xffU;
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break;
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case 2:
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*val = (data >> ((where & 2) << 3)) & 0xffffU;
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break;
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case 4:
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*val = data;
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t val)
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{
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uint32_t data;
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int shift;
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if (set_pci_configuration_address(bus->number, devfn, where) < 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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data = readl(PCICONFDREG);
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switch (size) {
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case 1:
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shift = (where & 3) << 3;
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data &= ~(0xffU << shift);
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data |= ((val & 0xffU) << shift);
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break;
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case 2:
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shift = (where & 2) << 3;
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data &= ~(0xffffU << shift);
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data |= ((val & 0xffffU) << shift);
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break;
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case 4:
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data = val;
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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writel(data, PCICONFDREG);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops vr41xx_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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