584 lines
16 KiB
C
584 lines
16 KiB
C
/*
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* drivers/pci/setup-bus.c
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*
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* Extruded from code written by
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* Dave Rusling (david.rusling@reo.mts.dec.com)
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* David Mosberger (davidm@cs.arizona.edu)
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* David Miller (davem@redhat.com)
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*
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* Support routines for initializing a PCI subsystem.
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*/
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/*
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* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* PCI-PCI bridges cleanup, sorted resource allocation.
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* Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* Converted to allocation in 3 passes, which gives
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* tighter packing. Prefetchable range support.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/cache.h>
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#include <linux/slab.h>
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static void pbus_assign_resources_sorted(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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struct resource *res;
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struct resource_list head, *list, *tmp;
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int idx;
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head.next = NULL;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 class = dev->class >> 8;
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/* Don't touch classless devices or host bridges or ioapics. */
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if (class == PCI_CLASS_NOT_DEFINED ||
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class == PCI_CLASS_BRIDGE_HOST)
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continue;
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/* Don't touch ioapic devices already enabled by firmware */
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if (class == PCI_CLASS_SYSTEM_PIC) {
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u16 command;
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pci_read_config_word(dev, PCI_COMMAND, &command);
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if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
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continue;
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}
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pdev_sort_resources(dev, &head);
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}
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for (list = head.next; list;) {
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res = list->res;
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idx = res - &list->dev->resource[0];
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if (pci_assign_resource(list->dev, idx)) {
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/* FIXME: get rid of this */
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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}
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tmp = list;
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list = list->next;
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kfree(tmp);
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}
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}
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void pci_setup_cardbus(struct pci_bus *bus)
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{
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struct pci_dev *bridge = bus->self;
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struct pci_bus_region region;
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dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
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pci_domain_nr(bus), bus->number);
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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if (bus->resource[0]->flags & IORESOURCE_IO) {
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/*
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* The IO resource is allocated a range twice as large as it
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* would normally need. This allows us to set both IO regs.
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*/
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dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
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region.start);
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pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
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region.end);
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}
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
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if (bus->resource[1]->flags & IORESOURCE_IO) {
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dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
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region.start);
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pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
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region.end);
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}
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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if (bus->resource[2]->flags & IORESOURCE_MEM) {
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dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
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region.start);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
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region.end);
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}
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
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if (bus->resource[3]->flags & IORESOURCE_MEM) {
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dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.end);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
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region.start);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
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region.end);
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}
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}
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EXPORT_SYMBOL(pci_setup_cardbus);
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/* Initialize bridges with base/limit values we have collected.
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PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
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requires that if there is no I/O ports or memory behind the
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bridge, corresponding range must be turned off by writing base
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value greater than limit to the bridge's base/limit registers.
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Note: care must be taken when updating I/O base/limit registers
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of bridges which support 32-bit I/O. This update requires two
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config space writes, so it's quite possible that an I/O window of
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the bridge will have some undesirable address (e.g. 0) after the
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first write. Ditto 64-bit prefetchable MMIO. */
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static void pci_setup_bridge(struct pci_bus *bus)
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{
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struct pci_dev *bridge = bus->self;
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struct pci_bus_region region;
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u32 l, bu, lu, io_upper16;
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dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
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pci_domain_nr(bus), bus->number);
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/* Set up the top and bottom of the PCI I/O segment for this bus. */
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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if (bus->resource[0]->flags & IORESOURCE_IO) {
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pci_read_config_dword(bridge, PCI_IO_BASE, &l);
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l &= 0xffff0000;
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l |= (region.start >> 8) & 0x00f0;
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l |= region.end & 0xf000;
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/* Set up upper 16 bits of I/O base/limit. */
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io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
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dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n",
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(unsigned long)region.start,
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(unsigned long)region.end);
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}
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else {
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/* Clear upper 16 bits of I/O base/limit. */
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io_upper16 = 0;
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l = 0x00f0;
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dev_info(&bridge->dev, " IO window: disabled\n");
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}
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/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
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pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
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/* Update lower 16 bits of I/O base/limit. */
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pci_write_config_dword(bridge, PCI_IO_BASE, l);
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/* Update upper 16 bits of I/O base/limit. */
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pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
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/* Set up the top and bottom of the PCI Memory segment
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for this bus. */
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
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if (bus->resource[1]->flags & IORESOURCE_MEM) {
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
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(unsigned long)region.start,
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(unsigned long)region.end);
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}
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else {
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l = 0x0000fff0;
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dev_info(&bridge->dev, " MEM window: disabled\n");
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}
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pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
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/* Clear out the upper 32 bits of PREF limit.
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If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
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disables PREF range, which is ok. */
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
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/* Set up PREF base/limit. */
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bu = lu = 0;
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pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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bu = upper_32_bits(region.start);
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lu = upper_32_bits(region.end);
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dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n",
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(unsigned long long)region.start,
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(unsigned long long)region.end);
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}
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else {
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l = 0x0000fff0;
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dev_info(&bridge->dev, " PREFETCH window: disabled\n");
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}
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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/* Set the upper 32 bits of PREF base & limit. */
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pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
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pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
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pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
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}
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/* Check whether the bridge supports optional I/O and
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prefetchable memory ranges. If not, the respective
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base/limit registers must be read-only and read as 0. */
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static void pci_bridge_check_ranges(struct pci_bus *bus)
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{
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u16 io;
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u32 pmem;
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struct pci_dev *bridge = bus->self;
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struct resource *b_res;
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b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
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b_res[1].flags |= IORESOURCE_MEM;
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pci_read_config_word(bridge, PCI_IO_BASE, &io);
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if (!io) {
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pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
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pci_read_config_word(bridge, PCI_IO_BASE, &io);
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pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
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}
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if (io)
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b_res[0].flags |= IORESOURCE_IO;
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/* DECchip 21050 pass 2 errata: the bridge may miss an address
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disconnect boundary by one PCI data phase.
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Workaround: do not use prefetching on this device. */
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if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
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return;
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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if (!pmem) {
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
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0xfff0fff0);
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pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
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}
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if (pmem)
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b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
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}
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/* Helper function for sizing routines: find first available
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bus resource of a given type. Note: we intentionally skip
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the bus resources which have already been assigned (that is,
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have non-NULL parent resource). */
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static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
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{
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int i;
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struct resource *r;
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unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
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IORESOURCE_PREFETCH;
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for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
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r = bus->resource[i];
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if (r == &ioport_resource || r == &iomem_resource)
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continue;
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if (r && (r->flags & type_mask) == type && !r->parent)
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return r;
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}
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return NULL;
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}
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/* Sizing the IO windows of the PCI-PCI bridge is trivial,
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since these windows have 4K granularity and the IO ranges
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of non-bridge PCI devices are limited to 256 bytes.
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We must be careful with the ISA aliasing though. */
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static void pbus_size_io(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
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unsigned long size = 0, size1 = 0;
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if (!b_res)
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return;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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unsigned long r_size;
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if (r->parent || !(r->flags & IORESOURCE_IO))
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continue;
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r_size = r->end - r->start + 1;
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if (r_size < 0x400)
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/* Might be re-aligned for ISA */
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size += r_size;
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else
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size1 += r_size;
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}
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}
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/* To be fixed in 2.5: we should have sort of HAVE_ISA
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flag in the struct pci_bus. */
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#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
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size = (size & 0xff) + ((size & ~0xffUL) << 2);
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#endif
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size = ALIGN(size + size1, 4096);
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if (!size) {
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b_res->flags = 0;
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return;
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}
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/* Alignment of the IO window is always 4K */
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b_res->start = 4096;
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b_res->end = b_res->start + size - 1;
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b_res->flags |= IORESOURCE_STARTALIGN;
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}
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/* Calculate the size of the bus and minimal alignment which
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guarantees that all child resources fit in this size. */
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static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
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{
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struct pci_dev *dev;
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resource_size_t min_align, align, size;
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resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
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int order, max_order;
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struct resource *b_res = find_free_bus_resource(bus, type);
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if (!b_res)
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return 0;
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memset(aligns, 0, sizeof(aligns));
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max_order = 0;
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size = 0;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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resource_size_t r_size;
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if (r->parent || (r->flags & mask) != type)
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continue;
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r_size = r->end - r->start + 1;
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/* For bridges size != alignment */
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align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
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order = __ffs(align) - 20;
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if (order > 11) {
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dev_warn(&dev->dev, "BAR %d too large: "
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"%#016llx-%#016llx\n", i,
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(unsigned long long)r->start,
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(unsigned long long)r->end);
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r->flags = 0;
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continue;
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}
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size += r_size;
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if (order < 0)
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order = 0;
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/* Exclude ranges with size > align from
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calculation of the alignment. */
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if (r_size == align)
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aligns[order] += align;
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if (order > max_order)
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max_order = order;
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}
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}
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align = 0;
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min_align = 0;
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for (order = 0; order <= max_order; order++) {
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#ifdef CONFIG_RESOURCES_64BIT
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resource_size_t align1 = 1ULL << (order + 20);
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#else
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resource_size_t align1 = 1U << (order + 20);
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#endif
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if (!align)
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min_align = align1;
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else if (ALIGN(align + min_align, min_align) < align1)
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min_align = align1 >> 1;
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align += aligns[order];
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}
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size = ALIGN(size, min_align);
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if (!size) {
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b_res->flags = 0;
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return 1;
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}
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b_res->start = min_align;
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b_res->end = size + min_align - 1;
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b_res->flags |= IORESOURCE_STARTALIGN;
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return 1;
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}
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static void pci_bus_size_cardbus(struct pci_bus *bus)
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{
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struct pci_dev *bridge = bus->self;
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struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
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u16 ctrl;
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/*
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* Reserve some resources for CardBus. We reserve
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* a fixed amount of bus space for CardBus bridges.
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*/
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b_res[0].start = 0;
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b_res[0].end = pci_cardbus_io_size - 1;
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b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
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b_res[1].start = 0;
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b_res[1].end = pci_cardbus_io_size - 1;
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b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
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/*
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* Check whether prefetchable memory is supported
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* by this bridge.
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*/
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pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
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if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
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ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
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pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
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pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
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}
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|
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/*
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* If we have prefetchable memory support, allocate
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* two regions. Otherwise, allocate one region of
|
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* twice the size.
|
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*/
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if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
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b_res[2].start = 0;
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b_res[2].end = pci_cardbus_mem_size - 1;
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b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
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b_res[3].start = 0;
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b_res[3].end = pci_cardbus_mem_size - 1;
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b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
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} else {
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b_res[3].start = 0;
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b_res[3].end = pci_cardbus_mem_size * 2 - 1;
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b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
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}
|
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}
|
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|
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void __ref pci_bus_size_bridges(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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unsigned long mask, prefmask;
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|
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list_for_each_entry(dev, &bus->devices, bus_list) {
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struct pci_bus *b = dev->subordinate;
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if (!b)
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continue;
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|
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switch (dev->class >> 8) {
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case PCI_CLASS_BRIDGE_CARDBUS:
|
|
pci_bus_size_cardbus(b);
|
|
break;
|
|
|
|
case PCI_CLASS_BRIDGE_PCI:
|
|
default:
|
|
pci_bus_size_bridges(b);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* The root bus? */
|
|
if (!bus->self)
|
|
return;
|
|
|
|
switch (bus->self->class >> 8) {
|
|
case PCI_CLASS_BRIDGE_CARDBUS:
|
|
/* don't size cardbuses yet. */
|
|
break;
|
|
|
|
case PCI_CLASS_BRIDGE_PCI:
|
|
pci_bridge_check_ranges(bus);
|
|
default:
|
|
pbus_size_io(bus);
|
|
/* If the bridge supports prefetchable range, size it
|
|
separately. If it doesn't, or its prefetchable window
|
|
has already been allocated by arch code, try
|
|
non-prefetchable range for both types of PCI memory
|
|
resources. */
|
|
mask = IORESOURCE_MEM;
|
|
prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
|
if (pbus_size_mem(bus, prefmask, prefmask))
|
|
mask = prefmask; /* Success, size non-prefetch only. */
|
|
pbus_size_mem(bus, mask, IORESOURCE_MEM);
|
|
break;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(pci_bus_size_bridges);
|
|
|
|
void __ref pci_bus_assign_resources(struct pci_bus *bus)
|
|
{
|
|
struct pci_bus *b;
|
|
struct pci_dev *dev;
|
|
|
|
pbus_assign_resources_sorted(bus);
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
b = dev->subordinate;
|
|
if (!b)
|
|
continue;
|
|
|
|
pci_bus_assign_resources(b);
|
|
|
|
switch (dev->class >> 8) {
|
|
case PCI_CLASS_BRIDGE_PCI:
|
|
pci_setup_bridge(b);
|
|
break;
|
|
|
|
case PCI_CLASS_BRIDGE_CARDBUS:
|
|
pci_setup_cardbus(b);
|
|
break;
|
|
|
|
default:
|
|
dev_info(&dev->dev, "not setting up bridge for bus "
|
|
"%04x:%02x\n", pci_domain_nr(b), b->number);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(pci_bus_assign_resources);
|
|
|
|
static void pci_bus_dump_res(struct pci_bus *bus)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
|
|
struct resource *res = bus->resource[i];
|
|
if (!res)
|
|
continue;
|
|
|
|
printk(KERN_INFO "bus: %02x index %x %s: [%llx, %llx]\n", bus->number, i, (res->flags & IORESOURCE_IO)? "io port":"mmio", res->start, res->end);
|
|
}
|
|
}
|
|
|
|
static void pci_bus_dump_resources(struct pci_bus *bus)
|
|
{
|
|
struct pci_bus *b;
|
|
struct pci_dev *dev;
|
|
|
|
|
|
pci_bus_dump_res(bus);
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
|
b = dev->subordinate;
|
|
if (!b)
|
|
continue;
|
|
|
|
pci_bus_dump_resources(b);
|
|
}
|
|
}
|
|
|
|
void __init
|
|
pci_assign_unassigned_resources(void)
|
|
{
|
|
struct pci_bus *bus;
|
|
|
|
/* Depth first, calculate sizes and alignments of all
|
|
subordinate buses. */
|
|
list_for_each_entry(bus, &pci_root_buses, node) {
|
|
pci_bus_size_bridges(bus);
|
|
}
|
|
/* Depth last, allocate resources and update the hardware. */
|
|
list_for_each_entry(bus, &pci_root_buses, node) {
|
|
pci_bus_assign_resources(bus);
|
|
pci_enable_bridges(bus);
|
|
}
|
|
|
|
/* dump the resource on buses */
|
|
list_for_each_entry(bus, &pci_root_buses, node) {
|
|
pci_bus_dump_resources(bus);
|
|
}
|
|
}
|