f24be42aab
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translation Fault Handling
- CAPP
- Memory Context ID
If a valid mm_struct is found the memory context id is used for each
transaction associated with the process handle. The PSL uses the
context ID to find the corresponding process element.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
[mpe: Fixup comment formatting, unsplit long strings]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
450 lines
16 KiB
Plaintext
450 lines
16 KiB
Plaintext
Coherent Accelerator Interface (CXL)
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====================================
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Introduction
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============
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The coherent accelerator interface is designed to allow the
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coherent connection of accelerators (FPGAs and other devices) to a
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POWER system. These devices need to adhere to the Coherent
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Accelerator Interface Architecture (CAIA).
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IBM refers to this as the Coherent Accelerator Processor Interface
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or CAPI. In the kernel it's referred to by the name CXL to avoid
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confusion with the ISDN CAPI subsystem.
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Coherent in this context means that the accelerator and CPUs can
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both access system memory directly and with the same effective
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addresses.
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Hardware overview
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=================
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POWER8/9 FPGA
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+----------+ +---------+
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| CPU | | AFU |
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+----------+ +---------+
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| PHB | | |
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| +------+ | PSL |
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| | CAPP |<------>| |
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+---+------+ PCIE +---------+
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The POWER8/9 chip has a Coherently Attached Processor Proxy (CAPP)
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unit which is part of the PCIe Host Bridge (PHB). This is managed
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by Linux by calls into OPAL. Linux doesn't directly program the
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CAPP.
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The FPGA (or coherently attached device) consists of two parts.
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The POWER Service Layer (PSL) and the Accelerator Function Unit
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(AFU). The AFU is used to implement specific functionality behind
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the PSL. The PSL, among other things, provides memory address
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translation services to allow each AFU direct access to userspace
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memory.
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The AFU is the core part of the accelerator (eg. the compression,
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crypto etc function). The kernel has no knowledge of the function
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of the AFU. Only userspace interacts directly with the AFU.
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The PSL provides the translation and interrupt services that the
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AFU needs. This is what the kernel interacts with. For example, if
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the AFU needs to read a particular effective address, it sends
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that address to the PSL, the PSL then translates it, fetches the
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data from memory and returns it to the AFU. If the PSL has a
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translation miss, it interrupts the kernel and the kernel services
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the fault. The context to which this fault is serviced is based on
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who owns that acceleration function.
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POWER8 <-----> PSL Version 8 is compliant to the CAIA Version 1.0.
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POWER9 <-----> PSL Version 9 is compliant to the CAIA Version 2.0.
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This PSL Version 9 provides new features such as:
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* Interaction with the nest MMU on the P9 chip.
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* Native DMA support.
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* Supports sending ASB_Notify messages for host thread wakeup.
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* Supports Atomic operations.
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* ....
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Cards with a PSL9 won't work on a POWER8 system and cards with a
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PSL8 won't work on a POWER9 system.
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AFU Modes
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=========
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There are two programming modes supported by the AFU. Dedicated
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and AFU directed. AFU may support one or both modes.
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When using dedicated mode only one MMU context is supported. In
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this mode, only one userspace process can use the accelerator at
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time.
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When using AFU directed mode, up to 16K simultaneous contexts can
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be supported. This means up to 16K simultaneous userspace
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applications may use the accelerator (although specific AFUs may
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support fewer). In this mode, the AFU sends a 16 bit context ID
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with each of its requests. This tells the PSL which context is
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associated with each operation. If the PSL can't translate an
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operation, the ID can also be accessed by the kernel so it can
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determine the userspace context associated with an operation.
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MMIO space
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==========
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A portion of the accelerator MMIO space can be directly mapped
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from the AFU to userspace. Either the whole space can be mapped or
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just a per context portion. The hardware is self describing, hence
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the kernel can determine the offset and size of the per context
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portion.
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Interrupts
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==========
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AFUs may generate interrupts that are destined for userspace. These
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are received by the kernel as hardware interrupts and passed onto
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userspace by a read syscall documented below.
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Data storage faults and error interrupts are handled by the kernel
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driver.
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Work Element Descriptor (WED)
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=============================
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The WED is a 64-bit parameter passed to the AFU when a context is
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started. Its format is up to the AFU hence the kernel has no
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knowledge of what it represents. Typically it will be the
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effective address of a work queue or status block where the AFU
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and userspace can share control and status information.
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User API
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========
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1. AFU character devices
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For AFUs operating in AFU directed mode, two character device
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files will be created. /dev/cxl/afu0.0m will correspond to a
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master context and /dev/cxl/afu0.0s will correspond to a slave
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context. Master contexts have access to the full MMIO space an
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AFU provides. Slave contexts have access to only the per process
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MMIO space an AFU provides.
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For AFUs operating in dedicated process mode, the driver will
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only create a single character device per AFU called
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/dev/cxl/afu0.0d. This will have access to the entire MMIO space
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that the AFU provides (like master contexts in AFU directed).
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The types described below are defined in include/uapi/misc/cxl.h
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The following file operations are supported on both slave and
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master devices.
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A userspace library libcxl is available here:
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https://github.com/ibm-capi/libcxl
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This provides a C interface to this kernel API.
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open
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----
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Opens the device and allocates a file descriptor to be used with
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the rest of the API.
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A dedicated mode AFU only has one context and only allows the
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device to be opened once.
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An AFU directed mode AFU can have many contexts, the device can be
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opened once for each context that is available.
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When all available contexts are allocated the open call will fail
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and return -ENOSPC.
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Note: IRQs need to be allocated for each context, which may limit
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the number of contexts that can be created, and therefore
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how many times the device can be opened. The POWER8 CAPP
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supports 2040 IRQs and 3 are used by the kernel, so 2037 are
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left. If 1 IRQ is needed per context, then only 2037
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contexts can be allocated. If 4 IRQs are needed per context,
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then only 2037/4 = 509 contexts can be allocated.
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ioctl
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-----
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CXL_IOCTL_START_WORK:
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Starts the AFU context and associates it with the current
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process. Once this ioctl is successfully executed, all memory
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mapped into this process is accessible to this AFU context
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using the same effective addresses. No additional calls are
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required to map/unmap memory. The AFU memory context will be
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updated as userspace allocates and frees memory. This ioctl
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returns once the AFU context is started.
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Takes a pointer to a struct cxl_ioctl_start_work:
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struct cxl_ioctl_start_work {
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__u64 flags;
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__u64 work_element_descriptor;
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__u64 amr;
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__s16 num_interrupts;
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__s16 reserved1;
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__s32 reserved2;
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__u64 reserved3;
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__u64 reserved4;
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__u64 reserved5;
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__u64 reserved6;
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};
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flags:
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Indicates which optional fields in the structure are
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valid.
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work_element_descriptor:
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The Work Element Descriptor (WED) is a 64-bit argument
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defined by the AFU. Typically this is an effective
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address pointing to an AFU specific structure
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describing what work to perform.
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amr:
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Authority Mask Register (AMR), same as the powerpc
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AMR. This field is only used by the kernel when the
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corresponding CXL_START_WORK_AMR value is specified in
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flags. If not specified the kernel will use a default
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value of 0.
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num_interrupts:
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Number of userspace interrupts to request. This field
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is only used by the kernel when the corresponding
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CXL_START_WORK_NUM_IRQS value is specified in flags.
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If not specified the minimum number required by the
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AFU will be allocated. The min and max number can be
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obtained from sysfs.
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reserved fields:
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For ABI padding and future extensions
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CXL_IOCTL_GET_PROCESS_ELEMENT:
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Get the current context id, also known as the process element.
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The value is returned from the kernel as a __u32.
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mmap
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----
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An AFU may have an MMIO space to facilitate communication with the
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AFU. If it does, the MMIO space can be accessed via mmap. The size
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and contents of this area are specific to the particular AFU. The
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size can be discovered via sysfs.
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In AFU directed mode, master contexts are allowed to map all of
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the MMIO space and slave contexts are allowed to only map the per
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process MMIO space associated with the context. In dedicated
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process mode the entire MMIO space can always be mapped.
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This mmap call must be done after the START_WORK ioctl.
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Care should be taken when accessing MMIO space. Only 32 and 64-bit
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accesses are supported by POWER8. Also, the AFU will be designed
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with a specific endianness, so all MMIO accesses should consider
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endianness (recommend endian(3) variants like: le64toh(),
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be64toh() etc). These endian issues equally apply to shared memory
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queues the WED may describe.
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read
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----
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Reads events from the AFU. Blocks if no events are pending
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(unless O_NONBLOCK is supplied). Returns -EIO in the case of an
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unrecoverable error or if the card is removed.
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read() will always return an integral number of events.
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The buffer passed to read() must be at least 4K bytes.
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The result of the read will be a buffer of one or more events,
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each event is of type struct cxl_event, of varying size.
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struct cxl_event {
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struct cxl_event_header header;
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union {
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struct cxl_event_afu_interrupt irq;
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struct cxl_event_data_storage fault;
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struct cxl_event_afu_error afu_error;
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};
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};
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The struct cxl_event_header is defined as:
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struct cxl_event_header {
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__u16 type;
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__u16 size;
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__u16 process_element;
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__u16 reserved1;
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};
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type:
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This defines the type of event. The type determines how
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the rest of the event is structured. These types are
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described below and defined by enum cxl_event_type.
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size:
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This is the size of the event in bytes including the
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struct cxl_event_header. The start of the next event can
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be found at this offset from the start of the current
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event.
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process_element:
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Context ID of the event.
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reserved field:
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For future extensions and padding.
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If the event type is CXL_EVENT_AFU_INTERRUPT then the event
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structure is defined as:
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struct cxl_event_afu_interrupt {
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__u16 flags;
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__u16 irq; /* Raised AFU interrupt number */
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__u32 reserved1;
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};
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flags:
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These flags indicate which optional fields are present
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in this struct. Currently all fields are mandatory.
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irq:
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The IRQ number sent by the AFU.
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reserved field:
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For future extensions and padding.
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If the event type is CXL_EVENT_DATA_STORAGE then the event
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structure is defined as:
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struct cxl_event_data_storage {
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__u16 flags;
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__u16 reserved1;
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__u32 reserved2;
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__u64 addr;
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__u64 dsisr;
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__u64 reserved3;
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};
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flags:
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These flags indicate which optional fields are present in
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this struct. Currently all fields are mandatory.
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address:
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The address that the AFU unsuccessfully attempted to
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access. Valid accesses will be handled transparently by the
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kernel but invalid accesses will generate this event.
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dsisr:
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This field gives information on the type of fault. It is a
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copy of the DSISR from the PSL hardware when the address
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fault occurred. The form of the DSISR is as defined in the
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CAIA.
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reserved fields:
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For future extensions
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If the event type is CXL_EVENT_AFU_ERROR then the event structure
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is defined as:
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struct cxl_event_afu_error {
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__u16 flags;
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__u16 reserved1;
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__u32 reserved2;
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__u64 error;
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};
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flags:
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These flags indicate which optional fields are present in
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this struct. Currently all fields are Mandatory.
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error:
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Error status from the AFU. Defined by the AFU.
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reserved fields:
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For future extensions and padding
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2. Card character device (powerVM guest only)
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In a powerVM guest, an extra character device is created for the
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card. The device is only used to write (flash) a new image on the
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FPGA accelerator. Once the image is written and verified, the
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device tree is updated and the card is reset to reload the updated
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image.
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open
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----
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Opens the device and allocates a file descriptor to be used with
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the rest of the API. The device can only be opened once.
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ioctl
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-----
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CXL_IOCTL_DOWNLOAD_IMAGE:
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CXL_IOCTL_VALIDATE_IMAGE:
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Starts and controls flashing a new FPGA image. Partial
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reconfiguration is not supported (yet), so the image must contain
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a copy of the PSL and AFU(s). Since an image can be quite large,
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the caller may have to iterate, splitting the image in smaller
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chunks.
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Takes a pointer to a struct cxl_adapter_image:
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struct cxl_adapter_image {
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__u64 flags;
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__u64 data;
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__u64 len_data;
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__u64 len_image;
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__u64 reserved1;
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__u64 reserved2;
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__u64 reserved3;
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__u64 reserved4;
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};
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flags:
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These flags indicate which optional fields are present in
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this struct. Currently all fields are mandatory.
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data:
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Pointer to a buffer with part of the image to write to the
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card.
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len_data:
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Size of the buffer pointed to by data.
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len_image:
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Full size of the image.
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Sysfs Class
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===========
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A cxl sysfs class is added under /sys/class/cxl to facilitate
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enumeration and tuning of the accelerators. Its layout is
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described in Documentation/ABI/testing/sysfs-class-cxl
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Udev rules
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==========
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The following udev rules could be used to create a symlink to the
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most logical chardev to use in any programming mode (afuX.Yd for
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dedicated, afuX.Ys for afu directed), since the API is virtually
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identical for each:
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SUBSYSTEM=="cxl", ATTRS{mode}=="dedicated_process", SYMLINK="cxl/%b"
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SUBSYSTEM=="cxl", ATTRS{mode}=="afu_directed", \
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KERNEL=="afu[0-9]*.[0-9]*s", SYMLINK="cxl/%b"
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