8a415c4be5
There is a bunch of old unused and ugly register definitions in the ColdFire 5282 header. Remove them. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
247 lines
9.1 KiB
C
247 lines
9.1 KiB
C
/****************************************************************************/
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/*
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* m528xsim.h -- ColdFire 5280/5282 System Integration Module support.
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*
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* (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com)
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*/
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/****************************************************************************/
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#ifndef m528xsim_h
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#define m528xsim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m528x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK MCF_CLK
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#include <asm/m52xxacr.h>
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/*
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* Define the 5280/5282 SIM register set addresses.
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*/
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#define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
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#define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
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#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
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#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
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#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
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#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
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#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_DCR (MCF_IPSBAR + 0x00000044) /* Control */
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#define MCFSIM_DACR0 (MCF_IPSBAR + 0x00000048) /* Base address 0 */
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#define MCFSIM_DMR0 (MCF_IPSBAR + 0x0000004c) /* Address mask 0 */
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#define MCFSIM_DACR1 (MCF_IPSBAR + 0x00000050) /* Base address 1 */
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#define MCFSIM_DMR1 (MCF_IPSBAR + 0x00000054) /* Address mask 1 */
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/*
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* DMA unit base addresses.
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*/
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#define MCFDMA_BASE0 (MCF_IPSBAR + 0x00000100)
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#define MCFDMA_BASE1 (MCF_IPSBAR + 0x00000140)
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#define MCFDMA_BASE2 (MCF_IPSBAR + 0x00000180)
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#define MCFDMA_BASE3 (MCF_IPSBAR + 0x000001C0)
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_IPSBAR + 0x00000200)
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#define MCFUART_BASE1 (MCF_IPSBAR + 0x00000240)
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#define MCFUART_BASE2 (MCF_IPSBAR + 0x00000280)
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/*
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* FEC ethernet module.
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*/
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#define MCFFEC_BASE0 (MCF_IPSBAR + 0x00001000)
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#define MCFFEC_SIZE0 0x800
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE (MCF_IPSBAR + 0x340)
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#define MCFQSPI_SIZE 0x40
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#define MCFQSPI_CS0 147
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#define MCFQSPI_CS1 148
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#define MCFQSPI_CS2 149
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#define MCFQSPI_CS3 150
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/*
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* GPIO registers
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*/
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#define MCFGPIO_PODR_A (MCF_IPSBAR + 0x00100000)
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#define MCFGPIO_PODR_B (MCF_IPSBAR + 0x00100001)
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#define MCFGPIO_PODR_C (MCF_IPSBAR + 0x00100002)
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#define MCFGPIO_PODR_D (MCF_IPSBAR + 0x00100003)
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#define MCFGPIO_PODR_E (MCF_IPSBAR + 0x00100004)
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#define MCFGPIO_PODR_F (MCF_IPSBAR + 0x00100005)
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#define MCFGPIO_PODR_G (MCF_IPSBAR + 0x00100006)
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#define MCFGPIO_PODR_H (MCF_IPSBAR + 0x00100007)
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#define MCFGPIO_PODR_J (MCF_IPSBAR + 0x00100008)
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#define MCFGPIO_PODR_DD (MCF_IPSBAR + 0x00100009)
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#define MCFGPIO_PODR_EH (MCF_IPSBAR + 0x0010000A)
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#define MCFGPIO_PODR_EL (MCF_IPSBAR + 0x0010000B)
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#define MCFGPIO_PODR_AS (MCF_IPSBAR + 0x0010000C)
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#define MCFGPIO_PODR_QS (MCF_IPSBAR + 0x0010000D)
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#define MCFGPIO_PODR_SD (MCF_IPSBAR + 0x0010000E)
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#define MCFGPIO_PODR_TC (MCF_IPSBAR + 0x0010000F)
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#define MCFGPIO_PODR_TD (MCF_IPSBAR + 0x00100010)
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#define MCFGPIO_PODR_UA (MCF_IPSBAR + 0x00100011)
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#define MCFGPIO_PDDR_A (MCF_IPSBAR + 0x00100014)
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#define MCFGPIO_PDDR_B (MCF_IPSBAR + 0x00100015)
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#define MCFGPIO_PDDR_C (MCF_IPSBAR + 0x00100016)
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#define MCFGPIO_PDDR_D (MCF_IPSBAR + 0x00100017)
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#define MCFGPIO_PDDR_E (MCF_IPSBAR + 0x00100018)
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#define MCFGPIO_PDDR_F (MCF_IPSBAR + 0x00100019)
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#define MCFGPIO_PDDR_G (MCF_IPSBAR + 0x0010001A)
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#define MCFGPIO_PDDR_H (MCF_IPSBAR + 0x0010001B)
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#define MCFGPIO_PDDR_J (MCF_IPSBAR + 0x0010001C)
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#define MCFGPIO_PDDR_DD (MCF_IPSBAR + 0x0010001D)
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#define MCFGPIO_PDDR_EH (MCF_IPSBAR + 0x0010001E)
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#define MCFGPIO_PDDR_EL (MCF_IPSBAR + 0x0010001F)
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#define MCFGPIO_PDDR_AS (MCF_IPSBAR + 0x00100020)
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#define MCFGPIO_PDDR_QS (MCF_IPSBAR + 0x00100021)
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#define MCFGPIO_PDDR_SD (MCF_IPSBAR + 0x00100022)
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#define MCFGPIO_PDDR_TC (MCF_IPSBAR + 0x00100023)
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#define MCFGPIO_PDDR_TD (MCF_IPSBAR + 0x00100024)
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#define MCFGPIO_PDDR_UA (MCF_IPSBAR + 0x00100025)
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#define MCFGPIO_PPDSDR_A (MCF_IPSBAR + 0x00100028)
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#define MCFGPIO_PPDSDR_B (MCF_IPSBAR + 0x00100029)
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#define MCFGPIO_PPDSDR_C (MCF_IPSBAR + 0x0010002A)
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#define MCFGPIO_PPDSDR_D (MCF_IPSBAR + 0x0010002B)
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#define MCFGPIO_PPDSDR_E (MCF_IPSBAR + 0x0010002C)
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#define MCFGPIO_PPDSDR_F (MCF_IPSBAR + 0x0010002D)
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#define MCFGPIO_PPDSDR_G (MCF_IPSBAR + 0x0010002E)
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#define MCFGPIO_PPDSDR_H (MCF_IPSBAR + 0x0010002F)
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#define MCFGPIO_PPDSDR_J (MCF_IPSBAR + 0x00100030)
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#define MCFGPIO_PPDSDR_DD (MCF_IPSBAR + 0x00100031)
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#define MCFGPIO_PPDSDR_EH (MCF_IPSBAR + 0x00100032)
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#define MCFGPIO_PPDSDR_EL (MCF_IPSBAR + 0x00100033)
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#define MCFGPIO_PPDSDR_AS (MCF_IPSBAR + 0x00100034)
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#define MCFGPIO_PPDSDR_QS (MCF_IPSBAR + 0x00100035)
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#define MCFGPIO_PPDSDR_SD (MCF_IPSBAR + 0x00100036)
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#define MCFGPIO_PPDSDR_TC (MCF_IPSBAR + 0x00100037)
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#define MCFGPIO_PPDSDR_TD (MCF_IPSBAR + 0x00100038)
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#define MCFGPIO_PPDSDR_UA (MCF_IPSBAR + 0x00100039)
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#define MCFGPIO_PCLRR_A (MCF_IPSBAR + 0x0010003C)
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#define MCFGPIO_PCLRR_B (MCF_IPSBAR + 0x0010003D)
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#define MCFGPIO_PCLRR_C (MCF_IPSBAR + 0x0010003E)
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#define MCFGPIO_PCLRR_D (MCF_IPSBAR + 0x0010003F)
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#define MCFGPIO_PCLRR_E (MCF_IPSBAR + 0x00100040)
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#define MCFGPIO_PCLRR_F (MCF_IPSBAR + 0x00100041)
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#define MCFGPIO_PCLRR_G (MCF_IPSBAR + 0x00100042)
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#define MCFGPIO_PCLRR_H (MCF_IPSBAR + 0x00100043)
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#define MCFGPIO_PCLRR_J (MCF_IPSBAR + 0x00100044)
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#define MCFGPIO_PCLRR_DD (MCF_IPSBAR + 0x00100045)
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#define MCFGPIO_PCLRR_EH (MCF_IPSBAR + 0x00100046)
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#define MCFGPIO_PCLRR_EL (MCF_IPSBAR + 0x00100047)
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#define MCFGPIO_PCLRR_AS (MCF_IPSBAR + 0x00100048)
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#define MCFGPIO_PCLRR_QS (MCF_IPSBAR + 0x00100049)
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#define MCFGPIO_PCLRR_SD (MCF_IPSBAR + 0x0010004A)
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#define MCFGPIO_PCLRR_TC (MCF_IPSBAR + 0x0010004B)
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#define MCFGPIO_PCLRR_TD (MCF_IPSBAR + 0x0010004C)
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#define MCFGPIO_PCLRR_UA (MCF_IPSBAR + 0x0010004D)
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#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
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#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
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#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
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#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
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#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
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#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
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#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
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#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
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#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
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#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
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#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
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/*
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* PIT timer base addresses.
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*/
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#define MCFPIT_BASE1 (MCF_IPSBAR + 0x00150000)
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#define MCFPIT_BASE2 (MCF_IPSBAR + 0x00160000)
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#define MCFPIT_BASE3 (MCF_IPSBAR + 0x00170000)
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#define MCFPIT_BASE4 (MCF_IPSBAR + 0x00180000)
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/*
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* Edge Port registers
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*/
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#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
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#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
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#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
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#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
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#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
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/*
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* Queued ADC registers
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*/
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#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
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#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
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#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
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#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
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/*
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* General Purpose Timers registers
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*/
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#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
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#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
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#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
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#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
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/*
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*
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* definitions for generic gpio support
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*
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_A /* port output data */
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#define MCFGPIO_PDDR MCFGPIO_PDDR_A /* port data direction */
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A/* port pin data */
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_A/* set output */
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_A /* clr output */
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCFGPIO_PIN_MAX 180
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/*
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* Reset Control Unit (relative to IPSBAR).
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*/
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#define MCF_RCR (MCF_IPSBAR + 0x110000)
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#define MCF_RSR (MCF_IPSBAR + 0x110001)
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/****************************************************************************/
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#endif /* m528xsim_h */
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