617 lines
17 KiB
C
617 lines
17 KiB
C
/*
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* Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
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* Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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*
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* Thanks :
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*
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* SiS Taiwan : for direct support and hardware.
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* Daniela Engert : for initial ATA100 advices and numerous others.
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* John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
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* for checking code correctness, providing patches.
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*
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*
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* Original tests and design on the SiS620 chipset.
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* ATA100 tests and design on the SiS735 chipset.
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* ATA16/33 support from specs
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* ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
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* ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
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*
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* Documentation:
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* SiS chipset documentation available under NDA to companies only
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* (not to individuals).
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*/
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/*
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* The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
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* SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
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* or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
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*
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* Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
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* starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
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* can figure out that we have a more modern and more capable 5513 by looking
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* for the respective NorthBridge IDs.
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*
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* Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
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* into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
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* ID, while the now ATA-133 capable 5513 still has the same PCI ID.
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* Fortunately the 5513 can be 'unmasked' by fiddling with some config space
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* bits, changing its device id to the true one - 5517 for 961 and 5518 for
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* 962/963.
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/hdreg.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include "ide-timing.h"
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/* registers layout and init values are chipset family dependant */
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#define ATA_16 0x01
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#define ATA_33 0x02
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#define ATA_66 0x03
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#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
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#define ATA_100 0x05
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#define ATA_133a 0x06 // SiS961b with 133 support
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#define ATA_133 0x07 // SiS962/963
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static u8 chipset_family;
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/*
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* Devices supported
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*/
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static const struct {
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const char *name;
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u16 host_id;
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u8 chipset_family;
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u8 flags;
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} SiSHostChipInfo[] = {
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{ "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
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{ "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
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{ "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
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{ "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
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{ "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
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{ "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
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{ "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
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{ "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
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{ "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
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{ "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
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{ "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
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{ "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
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{ "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
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{ "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
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{ "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
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{ "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
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{ "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
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{ "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
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{ "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
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{ "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
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{ "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
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{ "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
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{ "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
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{ "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
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{ "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
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};
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/* Cycle time bits and values vary across chip dma capabilities
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These three arrays hold the register layout and the values to set.
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Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
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/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
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static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
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static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
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static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
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{0,0,0,0,0,0,0}, /* no udma */
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{0,0,0,0,0,0,0}, /* no udma */
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{3,2,1,0,0,0,0}, /* ATA_33 */
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{7,5,3,2,1,0,0}, /* ATA_66 */
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{7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
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{11,7,5,4,2,1,0}, /* ATA_100 */
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{15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
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{15,10,7,5,3,2,1}, /* ATA_133 */
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};
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/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
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See SiS962 data sheet for more detail */
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static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
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{0,0,0,0,0,0,0}, /* no udma */
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{0,0,0,0,0,0,0}, /* no udma */
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{2,1,1,0,0,0,0},
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{4,3,2,1,0,0,0},
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{4,3,2,1,0,0,0},
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{6,4,3,1,1,1,0},
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{9,6,4,2,2,2,2},
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{9,6,4,2,2,2,2},
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};
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/* Initialize time, Active time, Recovery time vary across
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IDE clock settings. These 3 arrays hold the register value
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for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
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static u8 ini_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{2,1,0,0,0,1,0,0},
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{4,3,1,1,1,3,1,1},
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{4,3,1,1,1,3,1,1},
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{6,4,2,2,2,4,2,2},
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{9,6,3,3,3,6,3,3},
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{9,6,3,3,3,6,3,3},
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};
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static u8 act_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{9,9,9,2,2,7,2,2},
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{19,19,19,5,4,14,5,4},
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{19,19,19,5,4,14,5,4},
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{28,28,28,7,6,21,7,6},
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{38,38,38,10,9,28,10,9},
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{38,38,38,10,9,28,10,9},
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};
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static u8 rco_time_value[][8] = {
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{0,0,0,0,0,0,0,0},
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{0,0,0,0,0,0,0,0},
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{9,2,0,2,0,7,1,1},
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{19,5,1,5,2,16,3,2},
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{19,5,1,5,2,16,3,2},
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{30,9,3,9,4,25,6,4},
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{40,12,4,12,5,34,12,5},
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{40,12,4,12,5,34,12,5},
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};
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/*
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* Printing configuration
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*/
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/* Used for chipset type printing at boot time */
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static char* chipset_capability[] = {
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"ATA", "ATA 16",
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"ATA 33", "ATA 66",
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"ATA 100 (1st gen)", "ATA 100 (2nd gen)",
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"ATA 133 (1st gen)", "ATA 133 (2nd gen)"
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};
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/*
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* Configuration functions
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*/
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static u8 sis_ata133_get_base(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 reg54 = 0;
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pci_read_config_dword(dev, 0x54, ®54);
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return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
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}
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static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u16 t1 = 0;
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u8 drive_pci = 0x40 + drive->dn * 2;
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const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
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const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
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pci_read_config_word(dev, drive_pci, &t1);
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/* clear active/recovery timings */
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t1 &= ~0x070f;
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if (mode >= XFER_MW_DMA_0) {
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if (chipset_family > ATA_16)
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t1 &= ~0x8000; /* disable UDMA */
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t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
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} else
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t1 |= pio_timings[mode - XFER_PIO_0];
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pci_write_config_word(dev, drive_pci, t1);
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}
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static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u8 t1, drive_pci = 0x40 + drive->dn * 2;
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/* timing bits: 7:4 active 3:0 recovery */
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const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
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const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
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if (mode >= XFER_MW_DMA_0) {
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u8 t2 = 0;
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pci_read_config_byte(dev, drive_pci, &t2);
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t2 &= ~0x80; /* disable UDMA */
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pci_write_config_byte(dev, drive_pci, t2);
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t1 = mwdma_timings[mode - XFER_MW_DMA_0];
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} else
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t1 = pio_timings[mode - XFER_PIO_0];
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pci_write_config_byte(dev, drive_pci + 1, t1);
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}
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static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 t1 = 0;
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u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
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pci_read_config_dword(dev, drive_pci, &t1);
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t1 &= 0xc0c00fff;
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clk = (t1 & 0x08) ? ATA_133 : ATA_100;
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if (mode >= XFER_MW_DMA_0) {
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t1 &= ~0x04; /* disable UDMA */
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idx = mode - XFER_MW_DMA_0 + 5;
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} else
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idx = mode - XFER_PIO_0;
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t1 |= ini_time_value[clk][idx] << 12;
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t1 |= act_time_value[clk][idx] << 16;
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t1 |= rco_time_value[clk][idx] << 24;
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pci_write_config_dword(dev, drive_pci, t1);
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}
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static void sis_program_timings(ide_drive_t *drive, const u8 mode)
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{
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if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
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sis_ata16_program_timings(drive, mode);
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else if (chipset_family < ATA_133) /* ATA_100/133a */
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sis_ata100_program_timings(drive, mode);
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else /* ATA_133 */
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sis_ata133_program_timings(drive, mode);
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}
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static void config_drive_art_rwp (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u8 reg4bh = 0;
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u8 rw_prefetch = 0;
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pci_read_config_byte(dev, 0x4b, ®4bh);
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if (drive->media == ide_disk)
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rw_prefetch = 0x11 << drive->dn;
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if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
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pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
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}
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static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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config_drive_art_rwp(drive);
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sis_program_timings(drive, XFER_PIO_0 + pio);
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}
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static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 regdw = 0;
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u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
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pci_read_config_dword(dev, drive_pci, ®dw);
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regdw |= 0x04;
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regdw &= 0xfffff00f;
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/* check if ATA133 enable */
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clk = (regdw & 0x08) ? ATA_133 : ATA_100;
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idx = mode - XFER_UDMA_0;
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regdw |= cycle_time_value[clk][idx] << 4;
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regdw |= cvs_time_value[clk][idx] << 8;
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pci_write_config_dword(dev, drive_pci, regdw);
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}
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static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
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pci_read_config_byte(dev, drive_pci + 1, ®);
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/* force the UDMA bit on if we want to use UDMA */
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reg |= 0x80;
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/* clean reg cycle time bits */
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reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
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/* set reg cycle time bits */
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reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
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pci_write_config_byte(dev, drive_pci + 1, reg);
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}
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static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
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{
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if (chipset_family >= ATA_133) /* ATA_133 */
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sis_ata133_program_udma_timings(drive, mode);
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else /* ATA_33/66/100a/100/133a */
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sis_ata33_program_udma_timings(drive, mode);
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}
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static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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if (speed >= XFER_UDMA_0)
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sis_program_udma_timings(drive, speed);
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else
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sis_program_timings(drive, speed);
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}
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static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 regdw = 0;
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u8 drive_pci = sis_ata133_get_base(drive);
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pci_read_config_dword(dev, drive_pci, ®dw);
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/* if ATA133 disable, we should not set speed above UDMA5 */
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return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
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}
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/* Chip detection and general config */
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static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
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{
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struct pci_dev *host;
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int i = 0;
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chipset_family = 0;
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for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
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host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
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if (!host)
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continue;
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chipset_family = SiSHostChipInfo[i].chipset_family;
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/* Special case for SiS630 : 630S/ET is ATA_100a */
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if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
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if (host->revision >= 0x30)
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chipset_family = ATA_100a;
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}
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pci_dev_put(host);
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printk(KERN_INFO "SIS5513: %s %s controller\n",
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SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
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}
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if (!chipset_family) { /* Belongs to pci-quirks */
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u32 idemisc;
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u16 trueid;
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/* Disable ID masking and register remapping */
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pci_read_config_dword(dev, 0x54, &idemisc);
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pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
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pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
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pci_write_config_dword(dev, 0x54, idemisc);
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if (trueid == 0x5518) {
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printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
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chipset_family = ATA_133;
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/* Check for 5513 compability mapping
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* We must use this, else the port enabled code will fail,
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* as it expects the enablebits at 0x4a.
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*/
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if ((idemisc & 0x40000000) == 0) {
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pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
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printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
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}
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}
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}
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if (!chipset_family) { /* Belongs to pci-quirks */
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struct pci_dev *lpc_bridge;
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u16 trueid;
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u8 prefctl;
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u8 idecfg;
|
|
|
|
pci_read_config_byte(dev, 0x4a, &idecfg);
|
|
pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
|
|
pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
|
|
pci_write_config_byte(dev, 0x4a, idecfg);
|
|
|
|
if (trueid == 0x5517) { /* SiS 961/961B */
|
|
|
|
lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
|
|
pci_read_config_byte(dev, 0x49, &prefctl);
|
|
pci_dev_put(lpc_bridge);
|
|
|
|
if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
|
|
printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
|
|
chipset_family = ATA_133a;
|
|
} else {
|
|
printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
|
|
chipset_family = ATA_100;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!chipset_family)
|
|
return -1;
|
|
|
|
/* Make general config ops here
|
|
1/ tell IDE channels to operate in Compatibility mode only
|
|
2/ tell old chips to allow per drive IDE timings */
|
|
|
|
{
|
|
u8 reg;
|
|
u16 regw;
|
|
|
|
switch(chipset_family) {
|
|
case ATA_133:
|
|
/* SiS962 operation mode */
|
|
pci_read_config_word(dev, 0x50, ®w);
|
|
if (regw & 0x08)
|
|
pci_write_config_word(dev, 0x50, regw&0xfff7);
|
|
pci_read_config_word(dev, 0x52, ®w);
|
|
if (regw & 0x08)
|
|
pci_write_config_word(dev, 0x52, regw&0xfff7);
|
|
break;
|
|
case ATA_133a:
|
|
case ATA_100:
|
|
/* Fixup latency */
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
|
|
/* Set compatibility bit */
|
|
pci_read_config_byte(dev, 0x49, ®);
|
|
if (!(reg & 0x01)) {
|
|
pci_write_config_byte(dev, 0x49, reg|0x01);
|
|
}
|
|
break;
|
|
case ATA_100a:
|
|
case ATA_66:
|
|
/* Fixup latency */
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
|
|
|
|
/* On ATA_66 chips the bit was elsewhere */
|
|
pci_read_config_byte(dev, 0x52, ®);
|
|
if (!(reg & 0x04)) {
|
|
pci_write_config_byte(dev, 0x52, reg|0x04);
|
|
}
|
|
break;
|
|
case ATA_33:
|
|
/* On ATA_33 we didn't have a single bit to set */
|
|
pci_read_config_byte(dev, 0x09, ®);
|
|
if ((reg & 0x0f) != 0x00) {
|
|
pci_write_config_byte(dev, 0x09, reg&0xf0);
|
|
}
|
|
case ATA_16:
|
|
/* force per drive recovery and active timings
|
|
needed on ATA_33 and below chips */
|
|
pci_read_config_byte(dev, 0x52, ®);
|
|
if (!(reg & 0x08)) {
|
|
pci_write_config_byte(dev, 0x52, reg|0x08);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct sis_laptop {
|
|
u16 device;
|
|
u16 subvendor;
|
|
u16 subdevice;
|
|
};
|
|
|
|
static const struct sis_laptop sis_laptop[] = {
|
|
/* devid, subvendor, subdev */
|
|
{ 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
|
|
{ 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
|
|
{ 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
|
|
/* end marker */
|
|
{ 0, }
|
|
};
|
|
|
|
static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(hwif->dev);
|
|
const struct sis_laptop *lap = &sis_laptop[0];
|
|
u8 ata66 = 0;
|
|
|
|
while (lap->device) {
|
|
if (lap->device == pdev->device &&
|
|
lap->subvendor == pdev->subsystem_vendor &&
|
|
lap->subdevice == pdev->subsystem_device)
|
|
return ATA_CBL_PATA40_SHORT;
|
|
lap++;
|
|
}
|
|
|
|
if (chipset_family >= ATA_133) {
|
|
u16 regw = 0;
|
|
u16 reg_addr = hwif->channel ? 0x52: 0x50;
|
|
pci_read_config_word(pdev, reg_addr, ®w);
|
|
ata66 = (regw & 0x8000) ? 0 : 1;
|
|
} else if (chipset_family >= ATA_66) {
|
|
u8 reg48h = 0;
|
|
u8 mask = hwif->channel ? 0x20 : 0x10;
|
|
pci_read_config_byte(pdev, 0x48, ®48h);
|
|
ata66 = (reg48h & mask) ? 0 : 1;
|
|
}
|
|
|
|
return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
|
|
}
|
|
|
|
static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
|
|
{
|
|
u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
|
|
|
|
hwif->set_pio_mode = &sis_set_pio_mode;
|
|
hwif->set_dma_mode = &sis_set_dma_mode;
|
|
|
|
if (chipset_family >= ATA_133)
|
|
hwif->udma_filter = sis5513_ata133_udma_filter;
|
|
|
|
hwif->cable_detect = ata66_sis5513;
|
|
|
|
if (hwif->dma_base == 0)
|
|
return;
|
|
|
|
hwif->ultra_mask = udma_rates[chipset_family];
|
|
}
|
|
|
|
static const struct ide_port_info sis5513_chipset __devinitdata = {
|
|
.name = "SIS5513",
|
|
.init_chipset = init_chipset_sis5513,
|
|
.init_hwif = init_hwif_sis5513,
|
|
.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
|
|
.host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA |
|
|
IDE_HFLAG_BOOTABLE,
|
|
.pio_mask = ATA_PIO4,
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
};
|
|
|
|
static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
return ide_setup_pci_device(dev, &sis5513_chipset);
|
|
}
|
|
|
|
static const struct pci_device_id sis5513_pci_tbl[] = {
|
|
{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
|
|
{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
|
|
{ PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "SIS_IDE",
|
|
.id_table = sis5513_pci_tbl,
|
|
.probe = sis5513_init_one,
|
|
};
|
|
|
|
static int __init sis5513_ide_init(void)
|
|
{
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
module_init(sis5513_ide_init);
|
|
|
|
MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
|
|
MODULE_DESCRIPTION("PCI driver module for SIS IDE");
|
|
MODULE_LICENSE("GPL");
|
|
|
|
/*
|
|
* TODO:
|
|
* - CLEANUP
|
|
* - Use drivers/ide/ide-timing.h !
|
|
* - More checks in the config registers (force values instead of
|
|
* relying on the BIOS setting them correctly).
|
|
* - Further optimisations ?
|
|
* . for example ATA66+ regs 0x48 & 0x4A
|
|
*/
|