b97c74bddc
Fixes a sequencing bug in spi driver pxa2xx_spi.c in which the chip select for a transfer may be asserted before the clock polarity is set on the interface. As a result of this bug, the clock signal may have the wrong polarity at transfer start, so it may need to make an extra half transition before the intended clock/data signals begin. (This probably means all transfers are one bit out of sequence.) This only occurs on the first transfer following a change in clock polarity in systems using more than one more than one such polarity. The fix assures that the clock mode is properly set before asserting chip select. This bug was introduced in a patch merged on 2006/12/10, kernel 2.6.20. The patch defines an additional bit in: include/asm-arm/arch-pxa/regs-ssp.h for 2.6.25 and newer kernels but this addition must be made in: include/asm-arm/arch-pxa/pxa-regs.h for kernels between 2.6.20 and 2.6.24, inclusive Signed-off-by: Ned Forrester <nforrester@whoi.edu> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Cc: Russell King <rmk@arm.linux.org.uk> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
114 lines
5.7 KiB
C
114 lines
5.7 KiB
C
#ifndef __ASM_ARCH_REGS_SSP_H
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#define __ASM_ARCH_REGS_SSP_H
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/*
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* SSP Serial Port Registers
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* PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
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* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
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*/
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#define SSCR0 (0x00) /* SSP Control Register 0 */
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#define SSCR1 (0x04) /* SSP Control Register 1 */
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#define SSSR (0x08) /* SSP Status Register */
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#define SSITR (0x0C) /* SSP Interrupt Test Register */
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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#define SSTSS (0x38) /* SSP Timeslot Status */
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#define SSACD (0x3C) /* SSP Audio Clock Divider */
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/* Common PXA2xx bits first */
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#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
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#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
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#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
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#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
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#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
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#define SSCR0_National (0x2 << 4) /* National Microwire */
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#define SSCR0_ECS (1 << 6) /* External clock select */
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#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
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#if defined(CONFIG_PXA25x)
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#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
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#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
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#elif defined(CONFIG_PXA27x)
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#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
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#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
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#define SSCR0_EDSS (1 << 20) /* Extended data size select */
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#define SSCR0_NCS (1 << 21) /* Network clock select */
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#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
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#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
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#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
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#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
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#define SSCR0_ADC (1 << 30) /* Audio clock select */
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#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
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#endif
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#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
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#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
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#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
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#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
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#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
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#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
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#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
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#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
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#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
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#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
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#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
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#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
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#define SSSR_BSY (1 << 4) /* SSP Busy */
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#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
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#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
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#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
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#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
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#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
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#define SSCR0_NCS (1 << 21) /* Network Clock Select */
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#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
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/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
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#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
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#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
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#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
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#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
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#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
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#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
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#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
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#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
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#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
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#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
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#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
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#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
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#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
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#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
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#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
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#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
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#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
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#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
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#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
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#define SSSR_BCE (1 << 23) /* Bit Count Error */
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#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
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#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
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#define SSSR_EOC (1 << 20) /* End Of Chain */
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#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
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#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
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#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
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#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
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#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
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#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
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#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
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#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
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#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
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#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
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#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
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#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
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#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
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#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
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#endif /* __ASM_ARCH_REGS_SSP_H */
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