1467 lines
36 KiB
C
1467 lines
36 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2012 Michael Ellerman, IBM Corporation.
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* Copyright 2012 Benjamin Herrenschmidt, IBM Corporation.
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*/
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#include <linux/kernel.h>
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#include <linux/kvm_host.h>
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#include <linux/err.h>
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#include <linux/gfp.h>
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#include <linux/anon_inodes.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <asm/kvm_book3s.h>
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#include <asm/kvm_ppc.h>
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#include <asm/hvcall.h>
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#include <asm/xics.h>
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#include <asm/debugfs.h>
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#include <asm/time.h>
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#include <linux/seq_file.h>
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#include "book3s_xics.h"
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#if 1
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#define XICS_DBG(fmt...) do { } while (0)
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#else
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#define XICS_DBG(fmt...) trace_printk(fmt)
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#endif
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#define ENABLE_REALMODE true
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#define DEBUG_REALMODE false
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/*
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* LOCKING
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* =======
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*
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* Each ICS has a spin lock protecting the information about the IRQ
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* sources and avoiding simultaneous deliveries of the same interrupt.
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*
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* ICP operations are done via a single compare & swap transaction
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* (most ICP state fits in the union kvmppc_icp_state)
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*/
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/*
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* TODO
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* ====
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*
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* - To speed up resends, keep a bitmap of "resend" set bits in the
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* ICS
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*
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* - Speed up server# -> ICP lookup (array ? hash table ?)
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*
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* - Make ICS lockless as well, or at least a per-interrupt lock or hashed
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* locks array to improve scalability
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*/
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/* -- ICS routines -- */
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static void icp_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq, bool check_resend);
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/*
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* Return value ideally indicates how the interrupt was handled, but no
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* callers look at it (given that we don't implement KVM_IRQ_LINE_STATUS),
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* so just return 0.
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*/
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static int ics_deliver_irq(struct kvmppc_xics *xics, u32 irq, u32 level)
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{
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struct ics_irq_state *state;
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struct kvmppc_ics *ics;
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u16 src;
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u32 pq_old, pq_new;
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XICS_DBG("ics deliver %#x (level: %d)\n", irq, level);
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics) {
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XICS_DBG("ics_deliver_irq: IRQ 0x%06x not found !\n", irq);
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return -EINVAL;
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}
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state = &ics->irq_state[src];
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if (!state->exists)
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return -EINVAL;
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if (level == KVM_INTERRUPT_SET_LEVEL || level == KVM_INTERRUPT_SET)
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level = 1;
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else if (level == KVM_INTERRUPT_UNSET)
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level = 0;
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/*
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* Take other values the same as 1, consistent with original code.
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* maybe WARN here?
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*/
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if (!state->lsi && level == 0) /* noop for MSI */
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return 0;
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do {
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pq_old = state->pq_state;
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if (state->lsi) {
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if (level) {
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if (pq_old & PQ_PRESENTED)
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/* Setting already set LSI ... */
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return 0;
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pq_new = PQ_PRESENTED;
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} else
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pq_new = 0;
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} else
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pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED;
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} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
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/* Test P=1, Q=0, this is the only case where we present */
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if (pq_new == PQ_PRESENTED)
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icp_deliver_irq(xics, NULL, irq, false);
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/* Record which CPU this arrived on for passed-through interrupts */
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if (state->host_irq)
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state->intr_cpu = raw_smp_processor_id();
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return 0;
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}
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static void ics_check_resend(struct kvmppc_xics *xics, struct kvmppc_ics *ics,
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struct kvmppc_icp *icp)
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{
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int i;
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for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
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struct ics_irq_state *state = &ics->irq_state[i];
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if (state->resend) {
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XICS_DBG("resend %#x prio %#x\n", state->number,
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state->priority);
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icp_deliver_irq(xics, icp, state->number, true);
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}
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}
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}
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static bool write_xive(struct kvmppc_xics *xics, struct kvmppc_ics *ics,
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struct ics_irq_state *state,
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u32 server, u32 priority, u32 saved_priority)
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{
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bool deliver;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&ics->lock);
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state->server = server;
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state->priority = priority;
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state->saved_priority = saved_priority;
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deliver = false;
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if ((state->masked_pending || state->resend) && priority != MASKED) {
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state->masked_pending = 0;
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state->resend = 0;
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deliver = true;
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}
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arch_spin_unlock(&ics->lock);
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local_irq_restore(flags);
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return deliver;
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}
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int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, u32 server, u32 priority)
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{
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struct kvmppc_xics *xics = kvm->arch.xics;
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struct kvmppc_icp *icp;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u16 src;
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if (!xics)
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return -ENODEV;
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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return -EINVAL;
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state = &ics->irq_state[src];
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icp = kvmppc_xics_find_server(kvm, server);
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if (!icp)
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return -EINVAL;
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XICS_DBG("set_xive %#x server %#x prio %#x MP:%d RS:%d\n",
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irq, server, priority,
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state->masked_pending, state->resend);
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if (write_xive(xics, ics, state, server, priority, priority))
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icp_deliver_irq(xics, icp, irq, false);
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return 0;
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}
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int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server, u32 *priority)
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{
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struct kvmppc_xics *xics = kvm->arch.xics;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u16 src;
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unsigned long flags;
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if (!xics)
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return -ENODEV;
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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return -EINVAL;
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state = &ics->irq_state[src];
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local_irq_save(flags);
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arch_spin_lock(&ics->lock);
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*server = state->server;
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*priority = state->priority;
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arch_spin_unlock(&ics->lock);
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local_irq_restore(flags);
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return 0;
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}
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int kvmppc_xics_int_on(struct kvm *kvm, u32 irq)
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{
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struct kvmppc_xics *xics = kvm->arch.xics;
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struct kvmppc_icp *icp;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u16 src;
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if (!xics)
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return -ENODEV;
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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return -EINVAL;
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state = &ics->irq_state[src];
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icp = kvmppc_xics_find_server(kvm, state->server);
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if (!icp)
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return -EINVAL;
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if (write_xive(xics, ics, state, state->server, state->saved_priority,
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state->saved_priority))
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icp_deliver_irq(xics, icp, irq, false);
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return 0;
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}
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int kvmppc_xics_int_off(struct kvm *kvm, u32 irq)
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{
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struct kvmppc_xics *xics = kvm->arch.xics;
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struct kvmppc_ics *ics;
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struct ics_irq_state *state;
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u16 src;
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if (!xics)
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return -ENODEV;
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ics = kvmppc_xics_find_ics(xics, irq, &src);
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if (!ics)
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return -EINVAL;
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state = &ics->irq_state[src];
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write_xive(xics, ics, state, state->server, MASKED, state->priority);
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return 0;
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}
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/* -- ICP routines, including hcalls -- */
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static inline bool icp_try_update(struct kvmppc_icp *icp,
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union kvmppc_icp_state old,
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union kvmppc_icp_state new,
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bool change_self)
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{
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bool success;
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/* Calculate new output value */
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new.out_ee = (new.xisr && (new.pending_pri < new.cppr));
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/* Attempt atomic update */
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success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw;
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if (!success)
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goto bail;
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XICS_DBG("UPD [%04lx] - C:%02x M:%02x PP: %02x PI:%06x R:%d O:%d\n",
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icp->server_num,
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old.cppr, old.mfrr, old.pending_pri, old.xisr,
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old.need_resend, old.out_ee);
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XICS_DBG("UPD - C:%02x M:%02x PP: %02x PI:%06x R:%d O:%d\n",
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new.cppr, new.mfrr, new.pending_pri, new.xisr,
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new.need_resend, new.out_ee);
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/*
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* Check for output state update
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*
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* Note that this is racy since another processor could be updating
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* the state already. This is why we never clear the interrupt output
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* here, we only ever set it. The clear only happens prior to doing
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* an update and only by the processor itself. Currently we do it
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* in Accept (H_XIRR) and Up_Cppr (H_XPPR).
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*
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* We also do not try to figure out whether the EE state has changed,
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* we unconditionally set it if the new state calls for it. The reason
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* for that is that we opportunistically remove the pending interrupt
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* flag when raising CPPR, so we need to set it back here if an
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* interrupt is still pending.
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*/
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if (new.out_ee) {
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kvmppc_book3s_queue_irqprio(icp->vcpu,
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BOOK3S_INTERRUPT_EXTERNAL);
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if (!change_self)
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kvmppc_fast_vcpu_kick(icp->vcpu);
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}
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bail:
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return success;
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}
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static void icp_check_resend(struct kvmppc_xics *xics,
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struct kvmppc_icp *icp)
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{
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u32 icsid;
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/* Order this load with the test for need_resend in the caller */
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smp_rmb();
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for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) {
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struct kvmppc_ics *ics = xics->ics[icsid];
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if (!test_and_clear_bit(icsid, icp->resend_map))
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continue;
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if (!ics)
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continue;
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ics_check_resend(xics, ics, icp);
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}
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}
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static bool icp_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority,
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u32 *reject)
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{
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union kvmppc_icp_state old_state, new_state;
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bool success;
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XICS_DBG("try deliver %#x(P:%#x) to server %#lx\n", irq, priority,
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icp->server_num);
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do {
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old_state = new_state = READ_ONCE(icp->state);
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*reject = 0;
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/* See if we can deliver */
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success = new_state.cppr > priority &&
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new_state.mfrr > priority &&
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new_state.pending_pri > priority;
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/*
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* If we can, check for a rejection and perform the
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* delivery
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*/
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if (success) {
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*reject = new_state.xisr;
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new_state.xisr = irq;
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new_state.pending_pri = priority;
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} else {
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/*
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* If we failed to deliver we set need_resend
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* so a subsequent CPPR state change causes us
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* to try a new delivery.
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*/
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new_state.need_resend = true;
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}
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} while (!icp_try_update(icp, old_state, new_state, false));
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return success;
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}
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static void icp_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq, bool check_resend)
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{
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struct ics_irq_state *state;
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struct kvmppc_ics *ics;
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u32 reject;
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u16 src;
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unsigned long flags;
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/*
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* This is used both for initial delivery of an interrupt and
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* for subsequent rejection.
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*
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* Rejection can be racy vs. resends. We have evaluated the
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* rejection in an atomic ICP transaction which is now complete,
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* so potentially the ICP can already accept the interrupt again.
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*
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* So we need to retry the delivery. Essentially the reject path
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* boils down to a failed delivery. Always.
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*
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* Now the interrupt could also have moved to a different target,
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* thus we may need to re-do the ICP lookup as well
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*/
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again:
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/* Get the ICS state and lock it */
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ics = kvmppc_xics_find_ics(xics, new_irq, &src);
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if (!ics) {
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XICS_DBG("icp_deliver_irq: IRQ 0x%06x not found !\n", new_irq);
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return;
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}
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state = &ics->irq_state[src];
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/* Get a lock on the ICS */
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local_irq_save(flags);
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arch_spin_lock(&ics->lock);
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/* Get our server */
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if (!icp || state->server != icp->server_num) {
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icp = kvmppc_xics_find_server(xics->kvm, state->server);
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if (!icp) {
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pr_warn("icp_deliver_irq: IRQ 0x%06x server 0x%x not found !\n",
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new_irq, state->server);
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goto out;
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}
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}
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if (check_resend)
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if (!state->resend)
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goto out;
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/* Clear the resend bit of that interrupt */
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state->resend = 0;
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/*
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* If masked, bail out
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*
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* Note: PAPR doesn't mention anything about masked pending
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* when doing a resend, only when doing a delivery.
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*
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* However that would have the effect of losing a masked
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* interrupt that was rejected and isn't consistent with
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* the whole masked_pending business which is about not
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* losing interrupts that occur while masked.
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*
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* I don't differentiate normal deliveries and resends, this
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* implementation will differ from PAPR and not lose such
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* interrupts.
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*/
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if (state->priority == MASKED) {
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XICS_DBG("irq %#x masked pending\n", new_irq);
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state->masked_pending = 1;
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goto out;
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}
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/*
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* Try the delivery, this will set the need_resend flag
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* in the ICP as part of the atomic transaction if the
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* delivery is not possible.
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*
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* Note that if successful, the new delivery might have itself
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* rejected an interrupt that was "delivered" before we took the
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* ics spin lock.
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*
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* In this case we do the whole sequence all over again for the
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* new guy. We cannot assume that the rejected interrupt is less
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* favored than the new one, and thus doesn't need to be delivered,
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* because by the time we exit icp_try_to_deliver() the target
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* processor may well have alrady consumed & completed it, and thus
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* the rejected interrupt might actually be already acceptable.
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*/
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if (icp_try_to_deliver(icp, new_irq, state->priority, &reject)) {
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/*
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* Delivery was successful, did we reject somebody else ?
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*/
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if (reject && reject != XICS_IPI) {
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arch_spin_unlock(&ics->lock);
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local_irq_restore(flags);
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new_irq = reject;
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check_resend = 0;
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goto again;
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}
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} else {
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/*
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* We failed to deliver the interrupt we need to set the
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* resend map bit and mark the ICS state as needing a resend
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*/
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state->resend = 1;
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/*
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* Make sure when checking resend, we don't miss the resend
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* if resend_map bit is seen and cleared.
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*/
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smp_wmb();
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set_bit(ics->icsid, icp->resend_map);
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/*
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* If the need_resend flag got cleared in the ICP some time
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* between icp_try_to_deliver() atomic update and now, then
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* we know it might have missed the resend_map bit. So we
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* retry
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*/
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smp_mb();
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if (!icp->state.need_resend) {
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state->resend = 0;
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arch_spin_unlock(&ics->lock);
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local_irq_restore(flags);
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check_resend = 0;
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goto again;
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}
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}
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out:
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arch_spin_unlock(&ics->lock);
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local_irq_restore(flags);
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}
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|
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static void icp_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u8 new_cppr)
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{
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union kvmppc_icp_state old_state, new_state;
|
|
bool resend;
|
|
|
|
/*
|
|
* This handles several related states in one operation:
|
|
*
|
|
* ICP State: Down_CPPR
|
|
*
|
|
* Load CPPR with new value and if the XISR is 0
|
|
* then check for resends:
|
|
*
|
|
* ICP State: Resend
|
|
*
|
|
* If MFRR is more favored than CPPR, check for IPIs
|
|
* and notify ICS of a potential resend. This is done
|
|
* asynchronously (when used in real mode, we will have
|
|
* to exit here).
|
|
*
|
|
* We do not handle the complete Check_IPI as documented
|
|
* here. In the PAPR, this state will be used for both
|
|
* Set_MFRR and Down_CPPR. However, we know that we aren't
|
|
* changing the MFRR state here so we don't need to handle
|
|
* the case of an MFRR causing a reject of a pending irq,
|
|
* this will have been handled when the MFRR was set in the
|
|
* first place.
|
|
*
|
|
* Thus we don't have to handle rejects, only resends.
|
|
*
|
|
* When implementing real mode for HV KVM, resend will lead to
|
|
* a H_TOO_HARD return and the whole transaction will be handled
|
|
* in virtual mode.
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
/* Down_CPPR */
|
|
new_state.cppr = new_cppr;
|
|
|
|
/*
|
|
* Cut down Resend / Check_IPI / IPI
|
|
*
|
|
* The logic is that we cannot have a pending interrupt
|
|
* trumped by an IPI at this point (see above), so we
|
|
* know that either the pending interrupt is already an
|
|
* IPI (in which case we don't care to override it) or
|
|
* it's either more favored than us or non existent
|
|
*/
|
|
if (new_state.mfrr < new_cppr &&
|
|
new_state.mfrr <= new_state.pending_pri) {
|
|
WARN_ON(new_state.xisr != XICS_IPI &&
|
|
new_state.xisr != 0);
|
|
new_state.pending_pri = new_state.mfrr;
|
|
new_state.xisr = XICS_IPI;
|
|
}
|
|
|
|
/* Latch/clear resend bit */
|
|
resend = new_state.need_resend;
|
|
new_state.need_resend = 0;
|
|
|
|
} while (!icp_try_update(icp, old_state, new_state, true));
|
|
|
|
/*
|
|
* Now handle resend checks. Those are asynchronous to the ICP
|
|
* state update in HW (ie bus transactions) so we can handle them
|
|
* separately here too
|
|
*/
|
|
if (resend)
|
|
icp_check_resend(xics, icp);
|
|
}
|
|
|
|
static noinline unsigned long kvmppc_h_xirr(struct kvm_vcpu *vcpu)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 xirr;
|
|
|
|
/* First, remove EE from the processor */
|
|
kvmppc_book3s_dequeue_irqprio(icp->vcpu, BOOK3S_INTERRUPT_EXTERNAL);
|
|
|
|
/*
|
|
* ICP State: Accept_Interrupt
|
|
*
|
|
* Return the pending interrupt (if any) along with the
|
|
* current CPPR, then clear the XISR & set CPPR to the
|
|
* pending priority
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
xirr = old_state.xisr | (((u32)old_state.cppr) << 24);
|
|
if (!old_state.xisr)
|
|
break;
|
|
new_state.cppr = new_state.pending_pri;
|
|
new_state.pending_pri = 0xff;
|
|
new_state.xisr = 0;
|
|
|
|
} while (!icp_try_update(icp, old_state, new_state, true));
|
|
|
|
XICS_DBG("h_xirr vcpu %d xirr %#x\n", vcpu->vcpu_id, xirr);
|
|
|
|
return xirr;
|
|
}
|
|
|
|
static noinline int kvmppc_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
|
|
unsigned long mfrr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp;
|
|
u32 reject;
|
|
bool resend;
|
|
bool local;
|
|
|
|
XICS_DBG("h_ipi vcpu %d to server %lu mfrr %#lx\n",
|
|
vcpu->vcpu_id, server, mfrr);
|
|
|
|
icp = vcpu->arch.icp;
|
|
local = icp->server_num == server;
|
|
if (!local) {
|
|
icp = kvmppc_xics_find_server(vcpu->kvm, server);
|
|
if (!icp)
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
/*
|
|
* ICP state: Set_MFRR
|
|
*
|
|
* If the CPPR is more favored than the new MFRR, then
|
|
* nothing needs to be rejected as there can be no XISR to
|
|
* reject. If the MFRR is being made less favored then
|
|
* there might be a previously-rejected interrupt needing
|
|
* to be resent.
|
|
*
|
|
* ICP state: Check_IPI
|
|
*
|
|
* If the CPPR is less favored, then we might be replacing
|
|
* an interrupt, and thus need to possibly reject it.
|
|
*
|
|
* ICP State: IPI
|
|
*
|
|
* Besides rejecting any pending interrupts, we also
|
|
* update XISR and pending_pri to mark IPI as pending.
|
|
*
|
|
* PAPR does not describe this state, but if the MFRR is being
|
|
* made less favored than its earlier value, there might be
|
|
* a previously-rejected interrupt needing to be resent.
|
|
* Ideally, we would want to resend only if
|
|
* prio(pending_interrupt) < mfrr &&
|
|
* prio(pending_interrupt) < cppr
|
|
* where pending interrupt is the one that was rejected. But
|
|
* we don't have that state, so we simply trigger a resend
|
|
* whenever the MFRR is made less favored.
|
|
*/
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
/* Set_MFRR */
|
|
new_state.mfrr = mfrr;
|
|
|
|
/* Check_IPI */
|
|
reject = 0;
|
|
resend = false;
|
|
if (mfrr < new_state.cppr) {
|
|
/* Reject a pending interrupt if not an IPI */
|
|
if (mfrr <= new_state.pending_pri) {
|
|
reject = new_state.xisr;
|
|
new_state.pending_pri = mfrr;
|
|
new_state.xisr = XICS_IPI;
|
|
}
|
|
}
|
|
|
|
if (mfrr > old_state.mfrr) {
|
|
resend = new_state.need_resend;
|
|
new_state.need_resend = 0;
|
|
}
|
|
} while (!icp_try_update(icp, old_state, new_state, local));
|
|
|
|
/* Handle reject */
|
|
if (reject && reject != XICS_IPI)
|
|
icp_deliver_irq(xics, icp, reject, false);
|
|
|
|
/* Handle resend */
|
|
if (resend)
|
|
icp_check_resend(xics, icp);
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static int kvmppc_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server)
|
|
{
|
|
union kvmppc_icp_state state;
|
|
struct kvmppc_icp *icp;
|
|
|
|
icp = vcpu->arch.icp;
|
|
if (icp->server_num != server) {
|
|
icp = kvmppc_xics_find_server(vcpu->kvm, server);
|
|
if (!icp)
|
|
return H_PARAMETER;
|
|
}
|
|
state = READ_ONCE(icp->state);
|
|
kvmppc_set_gpr(vcpu, 4, ((u32)state.cppr << 24) | state.xisr);
|
|
kvmppc_set_gpr(vcpu, 5, state.mfrr);
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
|
|
{
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 reject;
|
|
|
|
XICS_DBG("h_cppr vcpu %d cppr %#lx\n", vcpu->vcpu_id, cppr);
|
|
|
|
/*
|
|
* ICP State: Set_CPPR
|
|
*
|
|
* We can safely compare the new value with the current
|
|
* value outside of the transaction as the CPPR is only
|
|
* ever changed by the processor on itself
|
|
*/
|
|
if (cppr > icp->state.cppr)
|
|
icp_down_cppr(xics, icp, cppr);
|
|
else if (cppr == icp->state.cppr)
|
|
return;
|
|
|
|
/*
|
|
* ICP State: Up_CPPR
|
|
*
|
|
* The processor is raising its priority, this can result
|
|
* in a rejection of a pending interrupt:
|
|
*
|
|
* ICP State: Reject_Current
|
|
*
|
|
* We can remove EE from the current processor, the update
|
|
* transaction will set it again if needed
|
|
*/
|
|
kvmppc_book3s_dequeue_irqprio(icp->vcpu, BOOK3S_INTERRUPT_EXTERNAL);
|
|
|
|
do {
|
|
old_state = new_state = READ_ONCE(icp->state);
|
|
|
|
reject = 0;
|
|
new_state.cppr = cppr;
|
|
|
|
if (cppr <= new_state.pending_pri) {
|
|
reject = new_state.xisr;
|
|
new_state.xisr = 0;
|
|
new_state.pending_pri = 0xff;
|
|
}
|
|
|
|
} while (!icp_try_update(icp, old_state, new_state, true));
|
|
|
|
/*
|
|
* Check for rejects. They are handled by doing a new delivery
|
|
* attempt (see comments in icp_deliver_irq).
|
|
*/
|
|
if (reject && reject != XICS_IPI)
|
|
icp_deliver_irq(xics, icp, reject, false);
|
|
}
|
|
|
|
static int ics_eoi(struct kvm_vcpu *vcpu, u32 irq)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *state;
|
|
u16 src;
|
|
u32 pq_old, pq_new;
|
|
|
|
/*
|
|
* ICS EOI handling: For LSI, if P bit is still set, we need to
|
|
* resend it.
|
|
*
|
|
* For MSI, we move Q bit into P (and clear Q). If it is set,
|
|
* resend it.
|
|
*/
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &src);
|
|
if (!ics) {
|
|
XICS_DBG("ios_eoi: IRQ 0x%06x not found !\n", irq);
|
|
return H_PARAMETER;
|
|
}
|
|
state = &ics->irq_state[src];
|
|
|
|
if (state->lsi)
|
|
pq_new = state->pq_state;
|
|
else
|
|
do {
|
|
pq_old = state->pq_state;
|
|
pq_new = pq_old >> 1;
|
|
} while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old);
|
|
|
|
if (pq_new & PQ_PRESENTED)
|
|
icp_deliver_irq(xics, icp, irq, false);
|
|
|
|
kvm_notify_acked_irq(vcpu->kvm, 0, irq);
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static noinline int kvmppc_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
u32 irq = xirr & 0x00ffffff;
|
|
|
|
XICS_DBG("h_eoi vcpu %d eoi %#lx\n", vcpu->vcpu_id, xirr);
|
|
|
|
/*
|
|
* ICP State: EOI
|
|
*
|
|
* Note: If EOI is incorrectly used by SW to lower the CPPR
|
|
* value (ie more favored), we do not check for rejection of
|
|
* a pending interrupt, this is a SW error and PAPR sepcifies
|
|
* that we don't have to deal with it.
|
|
*
|
|
* The sending of an EOI to the ICS is handled after the
|
|
* CPPR update
|
|
*
|
|
* ICP State: Down_CPPR which we handle
|
|
* in a separate function as it's shared with H_CPPR.
|
|
*/
|
|
icp_down_cppr(xics, icp, xirr >> 24);
|
|
|
|
/* IPIs have no EOI */
|
|
if (irq == XICS_IPI)
|
|
return H_SUCCESS;
|
|
|
|
return ics_eoi(vcpu, irq);
|
|
}
|
|
|
|
int kvmppc_xics_rm_complete(struct kvm_vcpu *vcpu, u32 hcall)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
|
|
XICS_DBG("XICS_RM: H_%x completing, act: %x state: %lx tgt: %p\n",
|
|
hcall, icp->rm_action, icp->rm_dbgstate.raw, icp->rm_dbgtgt);
|
|
|
|
if (icp->rm_action & XICS_RM_KICK_VCPU) {
|
|
icp->n_rm_kick_vcpu++;
|
|
kvmppc_fast_vcpu_kick(icp->rm_kick_target);
|
|
}
|
|
if (icp->rm_action & XICS_RM_CHECK_RESEND) {
|
|
icp->n_rm_check_resend++;
|
|
icp_check_resend(xics, icp->rm_resend_icp);
|
|
}
|
|
if (icp->rm_action & XICS_RM_NOTIFY_EOI) {
|
|
icp->n_rm_notify_eoi++;
|
|
kvm_notify_acked_irq(vcpu->kvm, 0, icp->rm_eoied_irq);
|
|
}
|
|
|
|
icp->rm_action = 0;
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_xics_rm_complete);
|
|
|
|
int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 req)
|
|
{
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
unsigned long res;
|
|
int rc = H_SUCCESS;
|
|
|
|
/* Check if we have an ICP */
|
|
if (!xics || !vcpu->arch.icp)
|
|
return H_HARDWARE;
|
|
|
|
/* These requests don't have real-mode implementations at present */
|
|
switch (req) {
|
|
case H_XIRR_X:
|
|
res = kvmppc_h_xirr(vcpu);
|
|
kvmppc_set_gpr(vcpu, 4, res);
|
|
kvmppc_set_gpr(vcpu, 5, get_tb());
|
|
return rc;
|
|
case H_IPOLL:
|
|
rc = kvmppc_h_ipoll(vcpu, kvmppc_get_gpr(vcpu, 4));
|
|
return rc;
|
|
}
|
|
|
|
/* Check for real mode returning too hard */
|
|
if (xics->real_mode && is_kvmppc_hv_enabled(vcpu->kvm))
|
|
return kvmppc_xics_rm_complete(vcpu, req);
|
|
|
|
switch (req) {
|
|
case H_XIRR:
|
|
res = kvmppc_h_xirr(vcpu);
|
|
kvmppc_set_gpr(vcpu, 4, res);
|
|
break;
|
|
case H_CPPR:
|
|
kvmppc_h_cppr(vcpu, kvmppc_get_gpr(vcpu, 4));
|
|
break;
|
|
case H_EOI:
|
|
rc = kvmppc_h_eoi(vcpu, kvmppc_get_gpr(vcpu, 4));
|
|
break;
|
|
case H_IPI:
|
|
rc = kvmppc_h_ipi(vcpu, kvmppc_get_gpr(vcpu, 4),
|
|
kvmppc_get_gpr(vcpu, 5));
|
|
break;
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_xics_hcall);
|
|
|
|
|
|
/* -- Initialisation code etc. -- */
|
|
|
|
static void xics_debugfs_irqmap(struct seq_file *m,
|
|
struct kvmppc_passthru_irqmap *pimap)
|
|
{
|
|
int i;
|
|
|
|
if (!pimap)
|
|
return;
|
|
seq_printf(m, "========\nPIRQ mappings: %d maps\n===========\n",
|
|
pimap->n_mapped);
|
|
for (i = 0; i < pimap->n_mapped; i++) {
|
|
seq_printf(m, "r_hwirq=%x, v_hwirq=%x\n",
|
|
pimap->mapped[i].r_hwirq, pimap->mapped[i].v_hwirq);
|
|
}
|
|
}
|
|
|
|
static int xics_debug_show(struct seq_file *m, void *private)
|
|
{
|
|
struct kvmppc_xics *xics = m->private;
|
|
struct kvm *kvm = xics->kvm;
|
|
struct kvm_vcpu *vcpu;
|
|
int icsid, i;
|
|
unsigned long flags;
|
|
unsigned long t_rm_kick_vcpu, t_rm_check_resend;
|
|
unsigned long t_rm_notify_eoi;
|
|
unsigned long t_reject, t_check_resend;
|
|
|
|
if (!kvm)
|
|
return 0;
|
|
|
|
t_rm_kick_vcpu = 0;
|
|
t_rm_notify_eoi = 0;
|
|
t_rm_check_resend = 0;
|
|
t_check_resend = 0;
|
|
t_reject = 0;
|
|
|
|
xics_debugfs_irqmap(m, kvm->arch.pimap);
|
|
|
|
seq_printf(m, "=========\nICP state\n=========\n");
|
|
|
|
kvm_for_each_vcpu(i, vcpu, kvm) {
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
union kvmppc_icp_state state;
|
|
|
|
if (!icp)
|
|
continue;
|
|
|
|
state.raw = READ_ONCE(icp->state.raw);
|
|
seq_printf(m, "cpu server %#lx XIRR:%#x PPRI:%#x CPPR:%#x MFRR:%#x OUT:%d NR:%d\n",
|
|
icp->server_num, state.xisr,
|
|
state.pending_pri, state.cppr, state.mfrr,
|
|
state.out_ee, state.need_resend);
|
|
t_rm_kick_vcpu += icp->n_rm_kick_vcpu;
|
|
t_rm_notify_eoi += icp->n_rm_notify_eoi;
|
|
t_rm_check_resend += icp->n_rm_check_resend;
|
|
t_check_resend += icp->n_check_resend;
|
|
t_reject += icp->n_reject;
|
|
}
|
|
|
|
seq_printf(m, "ICP Guest->Host totals: kick_vcpu=%lu check_resend=%lu notify_eoi=%lu\n",
|
|
t_rm_kick_vcpu, t_rm_check_resend,
|
|
t_rm_notify_eoi);
|
|
seq_printf(m, "ICP Real Mode totals: check_resend=%lu resend=%lu\n",
|
|
t_check_resend, t_reject);
|
|
for (icsid = 0; icsid <= KVMPPC_XICS_MAX_ICS_ID; icsid++) {
|
|
struct kvmppc_ics *ics = xics->ics[icsid];
|
|
|
|
if (!ics)
|
|
continue;
|
|
|
|
seq_printf(m, "=========\nICS state for ICS 0x%x\n=========\n",
|
|
icsid);
|
|
|
|
local_irq_save(flags);
|
|
arch_spin_lock(&ics->lock);
|
|
|
|
for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
|
|
struct ics_irq_state *irq = &ics->irq_state[i];
|
|
|
|
seq_printf(m, "irq 0x%06x: server %#x prio %#x save prio %#x pq_state %d resend %d masked pending %d\n",
|
|
irq->number, irq->server, irq->priority,
|
|
irq->saved_priority, irq->pq_state,
|
|
irq->resend, irq->masked_pending);
|
|
|
|
}
|
|
arch_spin_unlock(&ics->lock);
|
|
local_irq_restore(flags);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SHOW_ATTRIBUTE(xics_debug);
|
|
|
|
static void xics_debugfs_init(struct kvmppc_xics *xics)
|
|
{
|
|
char *name;
|
|
|
|
name = kasprintf(GFP_KERNEL, "kvm-xics-%p", xics);
|
|
if (!name) {
|
|
pr_err("%s: no memory for name\n", __func__);
|
|
return;
|
|
}
|
|
|
|
xics->dentry = debugfs_create_file(name, 0444, powerpc_debugfs_root,
|
|
xics, &xics_debug_fops);
|
|
|
|
pr_debug("%s: created %s\n", __func__, name);
|
|
kfree(name);
|
|
}
|
|
|
|
static struct kvmppc_ics *kvmppc_xics_create_ics(struct kvm *kvm,
|
|
struct kvmppc_xics *xics, int irq)
|
|
{
|
|
struct kvmppc_ics *ics;
|
|
int i, icsid;
|
|
|
|
icsid = irq >> KVMPPC_XICS_ICS_SHIFT;
|
|
|
|
mutex_lock(&kvm->lock);
|
|
|
|
/* ICS already exists - somebody else got here first */
|
|
if (xics->ics[icsid])
|
|
goto out;
|
|
|
|
/* Create the ICS */
|
|
ics = kzalloc(sizeof(struct kvmppc_ics), GFP_KERNEL);
|
|
if (!ics)
|
|
goto out;
|
|
|
|
ics->icsid = icsid;
|
|
|
|
for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
|
|
ics->irq_state[i].number = (icsid << KVMPPC_XICS_ICS_SHIFT) | i;
|
|
ics->irq_state[i].priority = MASKED;
|
|
ics->irq_state[i].saved_priority = MASKED;
|
|
}
|
|
smp_wmb();
|
|
xics->ics[icsid] = ics;
|
|
|
|
if (icsid > xics->max_icsid)
|
|
xics->max_icsid = icsid;
|
|
|
|
out:
|
|
mutex_unlock(&kvm->lock);
|
|
return xics->ics[icsid];
|
|
}
|
|
|
|
static int kvmppc_xics_create_icp(struct kvm_vcpu *vcpu, unsigned long server_num)
|
|
{
|
|
struct kvmppc_icp *icp;
|
|
|
|
if (!vcpu->kvm->arch.xics)
|
|
return -ENODEV;
|
|
|
|
if (kvmppc_xics_find_server(vcpu->kvm, server_num))
|
|
return -EEXIST;
|
|
|
|
icp = kzalloc(sizeof(struct kvmppc_icp), GFP_KERNEL);
|
|
if (!icp)
|
|
return -ENOMEM;
|
|
|
|
icp->vcpu = vcpu;
|
|
icp->server_num = server_num;
|
|
icp->state.mfrr = MASKED;
|
|
icp->state.pending_pri = MASKED;
|
|
vcpu->arch.icp = icp;
|
|
|
|
XICS_DBG("created server for vcpu %d\n", vcpu->vcpu_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
u64 kvmppc_xics_get_icp(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
union kvmppc_icp_state state;
|
|
|
|
if (!icp)
|
|
return 0;
|
|
state = icp->state;
|
|
return ((u64)state.cppr << KVM_REG_PPC_ICP_CPPR_SHIFT) |
|
|
((u64)state.xisr << KVM_REG_PPC_ICP_XISR_SHIFT) |
|
|
((u64)state.mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT) |
|
|
((u64)state.pending_pri << KVM_REG_PPC_ICP_PPRI_SHIFT);
|
|
}
|
|
|
|
int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval)
|
|
{
|
|
struct kvmppc_icp *icp = vcpu->arch.icp;
|
|
struct kvmppc_xics *xics = vcpu->kvm->arch.xics;
|
|
union kvmppc_icp_state old_state, new_state;
|
|
struct kvmppc_ics *ics;
|
|
u8 cppr, mfrr, pending_pri;
|
|
u32 xisr;
|
|
u16 src;
|
|
bool resend;
|
|
|
|
if (!icp || !xics)
|
|
return -ENOENT;
|
|
|
|
cppr = icpval >> KVM_REG_PPC_ICP_CPPR_SHIFT;
|
|
xisr = (icpval >> KVM_REG_PPC_ICP_XISR_SHIFT) &
|
|
KVM_REG_PPC_ICP_XISR_MASK;
|
|
mfrr = icpval >> KVM_REG_PPC_ICP_MFRR_SHIFT;
|
|
pending_pri = icpval >> KVM_REG_PPC_ICP_PPRI_SHIFT;
|
|
|
|
/* Require the new state to be internally consistent */
|
|
if (xisr == 0) {
|
|
if (pending_pri != 0xff)
|
|
return -EINVAL;
|
|
} else if (xisr == XICS_IPI) {
|
|
if (pending_pri != mfrr || pending_pri >= cppr)
|
|
return -EINVAL;
|
|
} else {
|
|
if (pending_pri >= mfrr || pending_pri >= cppr)
|
|
return -EINVAL;
|
|
ics = kvmppc_xics_find_ics(xics, xisr, &src);
|
|
if (!ics)
|
|
return -EINVAL;
|
|
}
|
|
|
|
new_state.raw = 0;
|
|
new_state.cppr = cppr;
|
|
new_state.xisr = xisr;
|
|
new_state.mfrr = mfrr;
|
|
new_state.pending_pri = pending_pri;
|
|
|
|
/*
|
|
* Deassert the CPU interrupt request.
|
|
* icp_try_update will reassert it if necessary.
|
|
*/
|
|
kvmppc_book3s_dequeue_irqprio(icp->vcpu, BOOK3S_INTERRUPT_EXTERNAL);
|
|
|
|
/*
|
|
* Note that if we displace an interrupt from old_state.xisr,
|
|
* we don't mark it as rejected. We expect userspace to set
|
|
* the state of the interrupt sources to be consistent with
|
|
* the ICP states (either before or afterwards, which doesn't
|
|
* matter). We do handle resends due to CPPR becoming less
|
|
* favoured because that is necessary to end up with a
|
|
* consistent state in the situation where userspace restores
|
|
* the ICS states before the ICP states.
|
|
*/
|
|
do {
|
|
old_state = READ_ONCE(icp->state);
|
|
|
|
if (new_state.mfrr <= old_state.mfrr) {
|
|
resend = false;
|
|
new_state.need_resend = old_state.need_resend;
|
|
} else {
|
|
resend = old_state.need_resend;
|
|
new_state.need_resend = 0;
|
|
}
|
|
} while (!icp_try_update(icp, old_state, new_state, false));
|
|
|
|
if (resend)
|
|
icp_check_resend(xics, icp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int xics_get_source(struct kvmppc_xics *xics, long irq, u64 addr)
|
|
{
|
|
int ret;
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *irqp;
|
|
u64 __user *ubufp = (u64 __user *) addr;
|
|
u16 idx;
|
|
u64 val, prio;
|
|
unsigned long flags;
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &idx);
|
|
if (!ics)
|
|
return -ENOENT;
|
|
|
|
irqp = &ics->irq_state[idx];
|
|
local_irq_save(flags);
|
|
arch_spin_lock(&ics->lock);
|
|
ret = -ENOENT;
|
|
if (irqp->exists) {
|
|
val = irqp->server;
|
|
prio = irqp->priority;
|
|
if (prio == MASKED) {
|
|
val |= KVM_XICS_MASKED;
|
|
prio = irqp->saved_priority;
|
|
}
|
|
val |= prio << KVM_XICS_PRIORITY_SHIFT;
|
|
if (irqp->lsi) {
|
|
val |= KVM_XICS_LEVEL_SENSITIVE;
|
|
if (irqp->pq_state & PQ_PRESENTED)
|
|
val |= KVM_XICS_PENDING;
|
|
} else if (irqp->masked_pending || irqp->resend)
|
|
val |= KVM_XICS_PENDING;
|
|
|
|
if (irqp->pq_state & PQ_PRESENTED)
|
|
val |= KVM_XICS_PRESENTED;
|
|
|
|
if (irqp->pq_state & PQ_QUEUED)
|
|
val |= KVM_XICS_QUEUED;
|
|
|
|
ret = 0;
|
|
}
|
|
arch_spin_unlock(&ics->lock);
|
|
local_irq_restore(flags);
|
|
|
|
if (!ret && put_user(val, ubufp))
|
|
ret = -EFAULT;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int xics_set_source(struct kvmppc_xics *xics, long irq, u64 addr)
|
|
{
|
|
struct kvmppc_ics *ics;
|
|
struct ics_irq_state *irqp;
|
|
u64 __user *ubufp = (u64 __user *) addr;
|
|
u16 idx;
|
|
u64 val;
|
|
u8 prio;
|
|
u32 server;
|
|
unsigned long flags;
|
|
|
|
if (irq < KVMPPC_XICS_FIRST_IRQ || irq >= KVMPPC_XICS_NR_IRQS)
|
|
return -ENOENT;
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &idx);
|
|
if (!ics) {
|
|
ics = kvmppc_xics_create_ics(xics->kvm, xics, irq);
|
|
if (!ics)
|
|
return -ENOMEM;
|
|
}
|
|
irqp = &ics->irq_state[idx];
|
|
if (get_user(val, ubufp))
|
|
return -EFAULT;
|
|
|
|
server = val & KVM_XICS_DESTINATION_MASK;
|
|
prio = val >> KVM_XICS_PRIORITY_SHIFT;
|
|
if (prio != MASKED &&
|
|
kvmppc_xics_find_server(xics->kvm, server) == NULL)
|
|
return -EINVAL;
|
|
|
|
local_irq_save(flags);
|
|
arch_spin_lock(&ics->lock);
|
|
irqp->server = server;
|
|
irqp->saved_priority = prio;
|
|
if (val & KVM_XICS_MASKED)
|
|
prio = MASKED;
|
|
irqp->priority = prio;
|
|
irqp->resend = 0;
|
|
irqp->masked_pending = 0;
|
|
irqp->lsi = 0;
|
|
irqp->pq_state = 0;
|
|
if (val & KVM_XICS_LEVEL_SENSITIVE)
|
|
irqp->lsi = 1;
|
|
/* If PENDING, set P in case P is not saved because of old code */
|
|
if (val & KVM_XICS_PRESENTED || val & KVM_XICS_PENDING)
|
|
irqp->pq_state |= PQ_PRESENTED;
|
|
if (val & KVM_XICS_QUEUED)
|
|
irqp->pq_state |= PQ_QUEUED;
|
|
irqp->exists = 1;
|
|
arch_spin_unlock(&ics->lock);
|
|
local_irq_restore(flags);
|
|
|
|
if (val & KVM_XICS_PENDING)
|
|
icp_deliver_irq(xics, NULL, irqp->number, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvmppc_xics_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level,
|
|
bool line_status)
|
|
{
|
|
struct kvmppc_xics *xics = kvm->arch.xics;
|
|
|
|
if (!xics)
|
|
return -ENODEV;
|
|
return ics_deliver_irq(xics, irq, level);
|
|
}
|
|
|
|
static int xics_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|
{
|
|
struct kvmppc_xics *xics = dev->private;
|
|
|
|
switch (attr->group) {
|
|
case KVM_DEV_XICS_GRP_SOURCES:
|
|
return xics_set_source(xics, attr->attr, attr->addr);
|
|
}
|
|
return -ENXIO;
|
|
}
|
|
|
|
static int xics_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|
{
|
|
struct kvmppc_xics *xics = dev->private;
|
|
|
|
switch (attr->group) {
|
|
case KVM_DEV_XICS_GRP_SOURCES:
|
|
return xics_get_source(xics, attr->attr, attr->addr);
|
|
}
|
|
return -ENXIO;
|
|
}
|
|
|
|
static int xics_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
|
|
{
|
|
switch (attr->group) {
|
|
case KVM_DEV_XICS_GRP_SOURCES:
|
|
if (attr->attr >= KVMPPC_XICS_FIRST_IRQ &&
|
|
attr->attr < KVMPPC_XICS_NR_IRQS)
|
|
return 0;
|
|
break;
|
|
}
|
|
return -ENXIO;
|
|
}
|
|
|
|
static void kvmppc_xics_free(struct kvm_device *dev)
|
|
{
|
|
struct kvmppc_xics *xics = dev->private;
|
|
int i;
|
|
struct kvm *kvm = xics->kvm;
|
|
|
|
debugfs_remove(xics->dentry);
|
|
|
|
if (kvm)
|
|
kvm->arch.xics = NULL;
|
|
|
|
for (i = 0; i <= xics->max_icsid; i++)
|
|
kfree(xics->ics[i]);
|
|
kfree(xics);
|
|
kfree(dev);
|
|
}
|
|
|
|
static int kvmppc_xics_create(struct kvm_device *dev, u32 type)
|
|
{
|
|
struct kvmppc_xics *xics;
|
|
struct kvm *kvm = dev->kvm;
|
|
int ret = 0;
|
|
|
|
xics = kzalloc(sizeof(*xics), GFP_KERNEL);
|
|
if (!xics)
|
|
return -ENOMEM;
|
|
|
|
dev->private = xics;
|
|
xics->dev = dev;
|
|
xics->kvm = kvm;
|
|
|
|
/* Already there ? */
|
|
if (kvm->arch.xics)
|
|
ret = -EEXIST;
|
|
else
|
|
kvm->arch.xics = xics;
|
|
|
|
if (ret) {
|
|
kfree(xics);
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
|
|
if (cpu_has_feature(CPU_FTR_ARCH_206) &&
|
|
cpu_has_feature(CPU_FTR_HVMODE)) {
|
|
/* Enable real mode support */
|
|
xics->real_mode = ENABLE_REALMODE;
|
|
xics->real_mode_dbg = DEBUG_REALMODE;
|
|
}
|
|
#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void kvmppc_xics_init(struct kvm_device *dev)
|
|
{
|
|
struct kvmppc_xics *xics = (struct kvmppc_xics *)dev->private;
|
|
|
|
xics_debugfs_init(xics);
|
|
}
|
|
|
|
struct kvm_device_ops kvm_xics_ops = {
|
|
.name = "kvm-xics",
|
|
.create = kvmppc_xics_create,
|
|
.init = kvmppc_xics_init,
|
|
.destroy = kvmppc_xics_free,
|
|
.set_attr = xics_set_attr,
|
|
.get_attr = xics_get_attr,
|
|
.has_attr = xics_has_attr,
|
|
};
|
|
|
|
int kvmppc_xics_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu,
|
|
u32 xcpu)
|
|
{
|
|
struct kvmppc_xics *xics = dev->private;
|
|
int r = -EBUSY;
|
|
|
|
if (dev->ops != &kvm_xics_ops)
|
|
return -EPERM;
|
|
if (xics->kvm != vcpu->kvm)
|
|
return -EPERM;
|
|
if (vcpu->arch.irq_type)
|
|
return -EBUSY;
|
|
|
|
r = kvmppc_xics_create_icp(vcpu, xcpu);
|
|
if (!r)
|
|
vcpu->arch.irq_type = KVMPPC_IRQ_XICS;
|
|
|
|
return r;
|
|
}
|
|
|
|
void kvmppc_xics_free_icp(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (!vcpu->arch.icp)
|
|
return;
|
|
kfree(vcpu->arch.icp);
|
|
vcpu->arch.icp = NULL;
|
|
vcpu->arch.irq_type = KVMPPC_IRQ_DEFAULT;
|
|
}
|
|
|
|
void kvmppc_xics_set_mapped(struct kvm *kvm, unsigned long irq,
|
|
unsigned long host_irq)
|
|
{
|
|
struct kvmppc_xics *xics = kvm->arch.xics;
|
|
struct kvmppc_ics *ics;
|
|
u16 idx;
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &idx);
|
|
if (!ics)
|
|
return;
|
|
|
|
ics->irq_state[idx].host_irq = host_irq;
|
|
ics->irq_state[idx].intr_cpu = -1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_xics_set_mapped);
|
|
|
|
void kvmppc_xics_clr_mapped(struct kvm *kvm, unsigned long irq,
|
|
unsigned long host_irq)
|
|
{
|
|
struct kvmppc_xics *xics = kvm->arch.xics;
|
|
struct kvmppc_ics *ics;
|
|
u16 idx;
|
|
|
|
ics = kvmppc_xics_find_ics(xics, irq, &idx);
|
|
if (!ics)
|
|
return;
|
|
|
|
ics->irq_state[idx].host_irq = 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvmppc_xics_clr_mapped);
|