38941522ec
In the clocksource driver, we didn't explicitly enable the clock. it makes the clk reference counter wrong. We didn't encounter any hang issue because the tick's clock input has been open and is shared by some other hardware components, but if we don't enable those components in kernel, in the stage of disabling unused clk in kernel boot, Linux tick hangs. This patch fixes it. it does an explicit prepare and enable to the clock input, and increases the usage counter of the clk. Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
234 lines
6.4 KiB
C
234 lines
6.4 KiB
C
/*
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* System timer for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/time.h>
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#define PRIMA2_CLOCK_FREQ 1000000
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#define SIRFSOC_TIMER_COUNTER_LO 0x0000
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#define SIRFSOC_TIMER_COUNTER_HI 0x0004
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#define SIRFSOC_TIMER_MATCH_0 0x0008
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#define SIRFSOC_TIMER_MATCH_1 0x000C
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#define SIRFSOC_TIMER_MATCH_2 0x0010
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#define SIRFSOC_TIMER_MATCH_3 0x0014
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#define SIRFSOC_TIMER_MATCH_4 0x0018
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#define SIRFSOC_TIMER_MATCH_5 0x001C
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#define SIRFSOC_TIMER_STATUS 0x0020
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#define SIRFSOC_TIMER_INT_EN 0x0024
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#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
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#define SIRFSOC_TIMER_DIV 0x002C
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#define SIRFSOC_TIMER_LATCH 0x0030
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#define SIRFSOC_TIMER_LATCHED_LO 0x0034
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#define SIRFSOC_TIMER_LATCHED_HI 0x0038
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#define SIRFSOC_TIMER_WDT_INDEX 5
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#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
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#define SIRFSOC_TIMER_REG_CNT 11
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static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
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SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
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SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
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SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
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SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
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};
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static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
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static void __iomem *sirfsoc_timer_base;
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/* timer0 interrupt handler */
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static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
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BIT(0)));
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/* clear timer0 interrupt */
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writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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/* read 64-bit timer counter */
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static cycle_t sirfsoc_timer_read(struct clocksource *cs)
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{
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u64 cycles;
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/* latch the 64-bit timer counter */
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writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
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sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
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cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
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cycles = (cycles << 32) |
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readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
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return cycles;
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}
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static int sirfsoc_timer_set_next_event(unsigned long delta,
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struct clock_event_device *ce)
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{
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unsigned long now, next;
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writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
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sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
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now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
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next = now + delta;
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writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
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writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
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sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
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now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
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return next - now > delta ? -ETIME : 0;
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}
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static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *ce)
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{
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u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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WARN_ON(1);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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writel_relaxed(val | BIT(0),
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sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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writel_relaxed(val & ~BIT(0),
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sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static void sirfsoc_clocksource_suspend(struct clocksource *cs)
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{
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int i;
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writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
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sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
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for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
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sirfsoc_timer_reg_val[i] =
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readl_relaxed(sirfsoc_timer_base +
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sirfsoc_timer_reg_list[i]);
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}
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static void sirfsoc_clocksource_resume(struct clocksource *cs)
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{
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int i;
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for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
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writel_relaxed(sirfsoc_timer_reg_val[i],
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sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
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writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
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sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
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writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
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sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
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}
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static struct clock_event_device sirfsoc_clockevent = {
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.name = "sirfsoc_clockevent",
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.rating = 200,
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sirfsoc_timer_set_mode,
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.set_next_event = sirfsoc_timer_set_next_event,
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};
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static struct clocksource sirfsoc_clocksource = {
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.name = "sirfsoc_clocksource",
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.rating = 200,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.read = sirfsoc_timer_read,
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.suspend = sirfsoc_clocksource_suspend,
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.resume = sirfsoc_clocksource_resume,
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};
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static struct irqaction sirfsoc_timer_irq = {
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.name = "sirfsoc_timer0",
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.flags = IRQF_TIMER,
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.irq = 0,
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.handler = sirfsoc_timer_interrupt,
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.dev_id = &sirfsoc_clockevent,
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};
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/* Overwrite weak default sched_clock with more precise one */
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static u64 notrace sirfsoc_read_sched_clock(void)
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{
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return sirfsoc_timer_read(NULL);
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}
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static void __init sirfsoc_clockevent_init(void)
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{
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sirfsoc_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
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2, -2);
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}
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/* initialize the kernel jiffy timer source */
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static void __init sirfsoc_prima2_timer_init(struct device_node *np)
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{
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unsigned long rate;
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struct clk *clk;
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clk = of_clk_get(np, 0);
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BUG_ON(IS_ERR(clk));
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BUG_ON(clk_prepare_enable(clk));
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rate = clk_get_rate(clk);
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BUG_ON(rate < PRIMA2_CLOCK_FREQ);
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BUG_ON(rate % PRIMA2_CLOCK_FREQ);
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sirfsoc_timer_base = of_iomap(np, 0);
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if (!sirfsoc_timer_base)
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panic("unable to map timer cpu registers\n");
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sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
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writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
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sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
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writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
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writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
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BUG_ON(clocksource_register_hz(&sirfsoc_clocksource,
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PRIMA2_CLOCK_FREQ));
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sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
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BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
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sirfsoc_clockevent_init();
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}
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CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer,
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"sirf,prima2-tick", sirfsoc_prima2_timer_init);
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