base: add more tests with exceptions

This commit is contained in:
Denis Drakhnia 2023-12-26 07:41:16 +02:00
parent eb760e4cd4
commit 7d33692be6
9 changed files with 358 additions and 15 deletions

72
tests/asm/base/excp-3.S Normal file
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@ -0,0 +1,72 @@
#include "test_start.S"
sys_rt_sigaction SIGSEGV, act
{
setwd wsz=8, nfx=1
rrd,0 %psp.lo, %g16
}
{
rrd,0 %psp.hi, %g16
std,2 %g16, 0, psp
}
{
addd,0 0, 0, %r0
addd,1 0, 0, %r1
std,2 %g16, 8, psp
addd,3 0, 0, %r2
}
{
ldd,0 0, mem, %r0
ldd,2 8, mem, %r1
ldd,3 16, mem, %r2
ldd,5 0, 0, %empty
}
sys_exit 1
#include "test_end.S"
sig_handler:
isa_version %g16
cmpbdb,0 %g16, 5, %pred0
ldd,0 8, psp, %g16
andd,0 %g16, (1ULL << 32) - 1, %g16
std,2 %g16, [ frame ]
sys_access_hw_stacks READ_PROCEDURE_STACK_EX, frame, buf, 64
{
ldd,0 [ mem ], %g16
ldd,2 [ buf ], %g17
}
assert_eq_i64(%g16, %g17)
{
ldd,0 [ mem + 8 ], %g16
ldd,2 8, buf, %g17 ? %pred0
ldd,3 16, buf, %g17 ? ~%pred0
}
assert_eq_i64(%g16, %g17)
{
ldd,0 [ mem + 16 ], %g16
ldd,2 [ buf + 32 ], %g17
}
assert_eq_i64(%g16, %g17)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
mem:
.quad 0xdeadbeef
.quad 0xbeefdead
.quad 0xaaaaaaaa
.data
.balign 8
buf:
.fill 64, 1, 0
size:
.quad 0
frame:
.quad 0
psp:
.quad 0
.quad 0

72
tests/asm/base/excp-4.S Normal file
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#include "test_start.S"
sys_rt_sigaction SIGSEGV, act
{
setwd wsz=8, nfx=1
rrd,0 %psp.lo, %g16
}
{
rrd,0 %psp.hi, %g16
std,2 %g16, 0, psp
}
{
addd,0 0, 0, %r0
addd,1 0, 0, %r1
std,2 %g16, 8, psp
addd,3 0, 0, %r2
}
{
ldd,0 0, 0, %empty
ldd,2 0, mem, %r0
ldd,3 8, mem, %r1
ldd,5 16, mem, %r2
}
sys_exit 1
#include "test_end.S"
sig_handler:
isa_version %g16
cmpbdb,0 %g16, 5, %pred0
ldd,0 8, psp, %g16
andd,0 %g16, (1ULL << 32) - 1, %g16
std,2 %g16, [ frame ]
sys_access_hw_stacks READ_PROCEDURE_STACK_EX, frame, buf, 64
{
ldd,0 [ mem ], %g16
ldd,2 [ buf ], %g17
}
assert_eq_i64(%g16, %g17)
{
ldd,0 [ mem + 8 ], %g16
ldd,2 8, buf, %g17 ? %pred0
ldd,3 16, buf, %g17 ? ~%pred0
}
assert_eq_i64(%g16, %g17)
{
ldd,0 [ mem + 16 ], %g16
ldd,2 [ buf + 32 ], %g17
}
assert_eq_i64(%g16, %g17)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
mem:
.quad 0xdeadbeef
.quad 0xbeefdead
.quad 0xaaaaaaaa
.data
.balign 8
buf:
.fill 64, 1, 0
size:
.quad 0
frame:
.quad 0
psp:
.quad 0
.quad 0

58
tests/asm/base/excp-5.S Normal file
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#include "test_start.S"
sys_rt_sigaction SIGSEGV, act
{
setwd wsz=8, nfx=1
rrd,0 %psp.lo, %g16
}
{
rrd,0 %psp.hi, %g16
std,2 %g16, 0, psp
}
{
addd,0 0, 0, %r0
addd,1 0, 0, %r1
std,2 %g16, 8, psp
}
{
addd,0 0, 0xdeadbeef, %r0
ldd,2 0, 0, %empty
addd,5 0, 0xdeadbeef, %r1
}
sys_exit 1
#include "test_end.S"
sig_handler:
isa_version %g16
cmpbdb,0 %g16, 5, %pred0
ldd,0 8, psp, %g16
andd,0 %g16, (1ULL << 32) - 1, %g16
std,2 %g16, [ frame ]
sys_access_hw_stacks READ_PROCEDURE_STACK_EX, frame, buf, 64
ldd,0 [ buf ], %g16
assert_eq_i64(%g16, 0xdeadbeef)
ldd,2 [ buf + 8 ], %g16 ? %pred0
ldd,3 [ buf + 16 ], %g16 ? ~%pred0
assert_eq_i64(%g16, 0xdeadbeef)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
.data
.balign 8
buf:
.fill 64, 1, 0
size:
.quad 0
frame:
.quad 0
psp:
.quad 0
.quad 0

59
tests/asm/base/excp-6.S Normal file
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@ -0,0 +1,59 @@
#include "test_start.S"
sys_rt_sigaction SIGILL, act
{
setwd wsz=8, nfx=1
rrd,0 %psp.lo, %g16
}
{
rrd,0 %psp.hi, %g16
std,2 %g16, 0, psp
}
{
addd,0 0, 0, %r0
addd,1 0, 0, %r1
std,2 %g16, 8, psp
}
invalid64 %g17
{
addd,0 0, 0xdeadbeef, %r0
addd,2 0, %g17, %empty
addd,5 0, 0xdeadbeef, %r1
}
sys_exit 1
#include "test_end.S"
sig_handler:
isa_version %g16
cmpbdb,0 %g16, 5, %pred0
ldd,0 8, psp, %g16
andd,0 %g16, (1ULL << 32) - 1, %g16
std,2 %g16, [ frame ]
sys_access_hw_stacks READ_PROCEDURE_STACK_EX, frame, buf, 64
ldd,0 [ buf ], %g16
assert_eq_i64(%g16, 0)
ldd,2 [ buf + 8 ], %g16 ? %pred0
ldd,3 [ buf + 16 ], %g16 ? ~%pred0
assert_eq_i64(%g16, 0)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
.data
.balign 8
buf:
.fill 64, 1, 0
size:
.quad 0
frame:
.quad 0
psp:
.quad 0
.quad 0

25
tests/asm/base/excp-7.S Normal file
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@ -0,0 +1,25 @@
#include "test_start.S"
sys_rt_sigaction SIGILL, act
addd,0 0, 1, %g16
invalid64 %g17
{
stb,2 %g16, [ flag ]
addd,5 %g17, 0, %empty
}
sys_exit 1
#include "test_end.S"
sig_handler:
ldb,0 [ flag ], %g16
assert_eq_i64(%g16, 0)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
.data
flag:
.byte 0

24
tests/asm/base/excp-8.S Normal file
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@ -0,0 +1,24 @@
#include "test_start.S"
sys_rt_sigaction SIGFPE, act
addd,0 0, 1, %g16
{
stb,2 %g16, [ flag ]
udivs,5 0, 0, %empty
}
sys_exit 1
#include "test_end.S"
sig_handler:
ldb,0 [ flag ], %g16
assert_eq_i64(%g16, 1)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
.data
flag:
.byte 0

26
tests/asm/base/excp-9.S Normal file
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#include "test_start.S"
sys_rt_sigaction SIGILL, act
addd,0 0, 1, %g16
invalid64 %g17
cmpedb,0 %g17, 0, %pred0
{
stb,2 %g16, [ flag ]
addd,0 0, 0, %empty ? %pred0
}
sys_exit 1
#include "test_end.S"
sig_handler:
ldb,0 [ flag ], %g16
assert_eq_i64(%g16, 0)
exit_with_code
.section ".rodata"
act:
init_sigaction sig_handler
.data
flag:
.byte 0

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@ -295,26 +295,26 @@
.macro isa_version dst .macro isa_version dst
{ {
rrd,0 %idr, SCRATCH_REG7 rrd,0 %idr, SCRATCH_REG0
addd,1 0, 0xff, \dst addd,1 0, 0xff, \dst
} }
{ {
andd,0 SCRATCH_REG7, 0xff, SCRATCH_REG7 andd,0 SCRATCH_REG0, 0xff, SCRATCH_REG0
} }
{ {
cmpedb,0 SCRATCH_REG7, MDL_E2S, SCRATCH_PREG0 cmpedb,0 SCRATCH_REG0, MDL_E2S, SCRATCH_PREG0
cmpedb,1 SCRATCH_REG7, MDL_E2SM, SCRATCH_PREG1 cmpedb,1 SCRATCH_REG0, MDL_E2SM, SCRATCH_PREG1
cmpedb,3 SCRATCH_REG7, MDL_E4S, SCRATCH_PREG2 cmpedb,3 SCRATCH_REG0, MDL_E4S, SCRATCH_PREG2
cmpedb,4 SCRATCH_REG7, MDL_E8S, SCRATCH_PREG3 cmpedb,4 SCRATCH_REG0, MDL_E8S, SCRATCH_PREG3
} }
{ {
cmpedb,0 SCRATCH_REG7, MDL_E1SP, SCRATCH_PREG4 cmpedb,0 SCRATCH_REG0, MDL_E1SP, SCRATCH_PREG4
cmpedb,1 SCRATCH_REG7, MDL_E8S2, SCRATCH_PREG5 cmpedb,1 SCRATCH_REG0, MDL_E8S2, SCRATCH_PREG5
cmpedb,3 SCRATCH_REG7, MDL_E12S, SCRATCH_PREG6 cmpedb,3 SCRATCH_REG0, MDL_E12S, SCRATCH_PREG6
cmpedb,4 SCRATCH_REG7, MDL_E16S, SCRATCH_PREG7 cmpedb,4 SCRATCH_REG0, MDL_E16S, SCRATCH_PREG7
} }
{ {
cmpedb,0 SCRATCH_REG7, MDL_E2S3, SCRATCH_PREG8 cmpedb,0 SCRATCH_REG0, MDL_E2S3, SCRATCH_PREG8
} }
{ {
addd,0 0, 2, \dst ? SCRATCH_PREG0 addd,0 0, 2, \dst ? SCRATCH_PREG0
@ -332,16 +332,16 @@
.endm .endm
.macro min_version ver .macro min_version ver
isa_version SCRATCH_REG0 isa_version SCRATCH_REG1
cmplsb,0 SCRATCH_REG0, \ver, SCRATCH_PREG0 cmplsb,0 SCRATCH_REG1, \ver, SCRATCH_PREG0
ibranch 0f ? ~SCRATCH_PREG0 ibranch 0f ? ~SCRATCH_PREG0
skip_test skip_test
0: 0:
.endm .endm
.macro max_version ver .macro max_version ver
isa_version SCRATCH_REG0 isa_version SCRATCH_REG1
cmplesb,0 SCRATCH_REG0, \ver, SCRATCH_PREG0 cmplesb,0 SCRATCH_REG1, \ver, SCRATCH_PREG0
ibranch 0f ? SCRATCH_PREG0 ibranch 0f ? SCRATCH_PREG0
skip_test skip_test
0: 0:

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@ -46,6 +46,13 @@ asm_tests = {
'signal-1': {}, 'signal-1': {},
'excp-1': {}, 'excp-1': {},
'excp-2': {}, 'excp-2': {},
'excp-3': {},
'excp-4': {},
'excp-5': {},
'excp-6': {},
'excp-7': {},
'excp-8': {},
'excp-9': {},
}, },
'win': { 'win': {
'setwd-1': {}, 'setwd-1': {},