2014-02-10 17:20:52 +01:00
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#include "macros.inc"
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2011-09-06 01:55:57 +02:00
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test_suite mmu
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2022-04-26 05:05:18 +02:00
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#if XCHAL_HAVE_PTP_MMU
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#define BASE 0x20000000
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#define TLB_BASE 0x80000000
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2019-02-18 16:19:02 +01:00
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2014-02-10 09:26:45 +01:00
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.purgem test_init
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2011-09-06 01:55:57 +02:00
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2014-05-20 22:50:12 +02:00
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.macro clean_tlb_way way, page_size, n_entries
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movi a2, \way
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movi a3, \page_size
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movi a4, \n_entries
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loop a4, 1f
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2011-09-06 01:55:57 +02:00
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idtlb a2
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2014-05-20 22:50:12 +02:00
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iitlb a2
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add a2, a2, a3
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1:
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.endm
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.macro test_init
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clean_tlb_way 0, 0x00001000, 4
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clean_tlb_way 1, 0x00001000, 4
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clean_tlb_way 2, 0x00001000, 4
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clean_tlb_way 3, 0x00001000, 4
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clean_tlb_way 4, 0x00100000, 4
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movi a2, 0x00000007
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2011-09-06 01:55:57 +02:00
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idtlb a2
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2014-05-20 22:50:12 +02:00
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movi a2, 0x00000008
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2011-09-06 01:55:57 +02:00
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idtlb a2
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2014-05-20 22:50:12 +02:00
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movi a2, 0x00000009
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2011-09-06 01:55:57 +02:00
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idtlb a2
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2022-04-26 05:05:18 +02:00
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#if XCHAL_HAVE_SPANNING_WAY
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movi a2, BASE | XCHAL_SPANNING_WAY
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idtlb a2
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iitlb a2
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movi a2, TLB_BASE | XCHAL_SPANNING_WAY
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idtlb a2
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iitlb a2
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movi a2, TLB_BASE
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wsr a2, ptevaddr
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#endif
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2011-09-06 01:55:57 +02:00
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.endm
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test tlb_group
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movi a2, 0x04000002 /* PPN */
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200004 /* VPN */
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2011-09-06 01:55:57 +02:00
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wdtlb a2, a3
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witlb a2, a3
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movi a3, 0x00200004
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rdtlb0 a1, a3
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ritlb0 a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01000001
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2011-09-06 01:55:57 +02:00
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assert eq, a1, a3
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assert eq, a2, a3
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movi a3, 0x00200004
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rdtlb1 a1, a3
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ritlb1 a2, a3
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movi a3, 0x04000002
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assert eq, a1, a3
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assert eq, a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01234567
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2011-09-06 01:55:57 +02:00
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pdtlb a1, a3
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pitlb a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01234014
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2011-09-06 01:55:57 +02:00
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assert eq, a1, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x0123400c
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2011-09-06 01:55:57 +02:00
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assert eq, a2, a3
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movi a3, 0x00200004
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idtlb a3
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iitlb a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01234567
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2011-09-06 01:55:57 +02:00
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pdtlb a1, a3
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pitlb a2, a3
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movi a3, 0x00000010
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and a1, a1, a3
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assert eqi, a1, 0
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movi a3, 0x00000008
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and a2, a2, a3
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assert eqi, a2, 0
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test_end
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test itlb_miss
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set_vector kernel, 1f
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x00100000
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2011-09-06 01:55:57 +02:00
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jx a3
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test_fail
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1:
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rsr a2, excvaddr
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 16
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assert eq, a2, a3
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test_end
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test dtlb_miss
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set_vector kernel, 1f
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x00100000
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2011-09-06 01:55:57 +02:00
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l8ui a2, a3, 0
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test_fail
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1:
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rsr a2, excvaddr
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 24
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assert eq, a2, a3
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test_end
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test itlb_multi_hit
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set_vector kernel, 1f
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movi a2, 0x04000002 /* PPN */
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movi a3, 0xf0000004 /* VPN */
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witlb a2, a3
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movi a3, 0xf0000000
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pitlb a2, a3
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test_fail
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1:
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rsr a2, exccause
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movi a3, 17
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assert eq, a2, a3
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test_end
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test dtlb_multi_hit
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set_vector kernel, 1f
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movi a2, 0x04000002 /* PPN */
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200004 /* VPN */
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2011-09-06 01:55:57 +02:00
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wdtlb a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200007 /* VPN */
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2011-09-06 01:55:57 +02:00
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wdtlb a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200000
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2011-09-06 01:55:57 +02:00
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pdtlb a2, a3
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test_fail
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1:
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rsr a2, exccause
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movi a3, 25
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assert eq, a2, a3
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test_end
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test inst_fetch_privilege
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set_vector kernel, 3f
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movi a2, 0x4004f
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wsr a2, ps
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1:
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isync
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nop
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2:
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test_fail
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3:
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movi a1, 1b
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rsr a2, excvaddr
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rsr a3, epc1
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assert ge, a2, a1
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assert ge, a3, a1
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movi a1, 2b
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assert lt, a2, a1
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assert lt, a3, a1
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rsr a2, exccause
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movi a3, 18
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assert eq, a2, a3
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rsr a2, ps
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movi a3, 0x4005f
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assert eq, a2, a3
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test_end
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test load_store_privilege
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set_vector kernel, 2f
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movi a3, 10f
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pitlb a3, a3
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ritlb1 a2, a3
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movi a1, 0x10
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or a2, a2, a1
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movi a1, 0x000ff000
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and a3, a3, a1
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movi a1, 4
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or a3, a3, a1
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2022-04-26 05:05:18 +02:00
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movi a5, BASE
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add a3, a3, a5
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2011-09-06 01:55:57 +02:00
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witlb a2, a3
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movi a3, 10f
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movi a1, 0x000fffff
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and a1, a3, a1
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2022-04-26 05:05:18 +02:00
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add a1, a1, a5
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2011-09-06 01:55:57 +02:00
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movi a2, 0x04000003 /* PPN */
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200004 /* VPN */
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2011-09-06 01:55:57 +02:00
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wdtlb a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200001
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2011-09-06 01:55:57 +02:00
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movi a2, 0x4004f
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jx a1
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10:
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wsr a2, ps
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isync
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1:
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l8ui a2, a3, 0
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test_fail
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2:
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rsr a2, excvaddr
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assert eq, a2, a3
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rsr a2, epc1
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movi a3, 1b
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movi a1, 0x000fffff
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and a3, a3, a1
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2022-04-26 05:05:18 +02:00
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add a3, a3, a5
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2011-09-06 01:55:57 +02:00
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 26
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assert eq, a2, a3
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rsr a2, ps
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movi a3, 0x4005f
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assert eq, a2, a3
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test_end
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test cring_load_store_privilege
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set_vector kernel, 0
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set_vector double, 2f
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movi a2, 0x04000003 /* PPN */
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200004 /* VPN */
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2011-09-06 01:55:57 +02:00
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wdtlb a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200004
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2011-09-06 01:55:57 +02:00
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movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
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wsr a2, ps
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isync
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l8ui a2, a3, 0 /* cring used */
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1:
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l32e a2, a3, -4 /* ring used */
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test_fail
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2:
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rsr a2, excvaddr
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addi a2, a2, 4
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assert eq, a2, a3
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rsr a2, depc
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 26
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assert eq, a2, a3
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rsr a2, ps
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movi a3, 0x4005f
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assert eq, a2, a3
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test_end
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test inst_fetch_prohibited
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set_vector kernel, 2f
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movi a3, 10f
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pitlb a3, a3
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ritlb1 a2, a3
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movi a1, 0xfffff000
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and a2, a2, a1
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movi a1, 0x4
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or a2, a2, a1
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movi a1, 0x000ff000
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and a3, a3, a1
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movi a1, 4
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or a3, a3, a1
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2022-04-26 05:05:18 +02:00
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movi a5, BASE
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add a3, a3, a5
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2011-09-06 01:55:57 +02:00
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witlb a2, a3
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movi a3, 10f
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movi a1, 0x000fffff
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and a1, a3, a1
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2022-04-26 05:05:18 +02:00
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add a1, a1, a5
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2011-09-06 01:55:57 +02:00
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jx a1
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.align 4
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10:
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nop
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test_fail
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2:
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rsr a2, excvaddr
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assert eq, a2, a1
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rsr a2, epc1
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assert eq, a2, a1
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rsr a2, exccause
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movi a3, 20
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assert eq, a2, a3
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test_end
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test load_prohibited
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set_vector kernel, 2f
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movi a2, 0x0400000c /* PPN */
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200004 /* VPN */
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2011-09-06 01:55:57 +02:00
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wdtlb a2, a3
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2022-04-26 05:05:18 +02:00
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movi a3, BASE + 0x01200002
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2011-09-06 01:55:57 +02:00
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1:
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l8ui a2, a3, 0
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test_fail
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2:
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rsr a2, excvaddr
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assert eq, a2, a3
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rsr a2, epc1
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movi a3, 1b
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assert eq, a2, a3
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rsr a2, exccause
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movi a3, 28
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assert eq, a2, a3
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test_end
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test store_prohibited
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set_vector kernel, 2f
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|
|
|
movi a2, 0x04000001 /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x01200004 /* VPN */
|
2011-09-06 01:55:57 +02:00
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x01200003
|
2011-09-06 01:55:57 +02:00
|
|
|
l8ui a2, a3, 0
|
|
|
|
|
1:
|
|
|
|
|
s8i a2, a3, 0
|
|
|
|
|
test_fail
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
|
|
|
|
movi a3, 1b
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 29
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
test_end
|
|
|
|
|
|
2012-05-27 16:34:54 +02:00
|
|
|
/* Set up page table entry vaddr->paddr, ring=pte_ring, attr=pte_attr
|
|
|
|
|
* and DTLB way 7 to cover this PTE, ring=pt_ring, attr=pt_attr
|
|
|
|
|
*/
|
|
|
|
|
.macro pt_setup pt_ring, pt_attr, pte_ring, vaddr, paddr, pte_attr
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, TLB_BASE
|
2011-09-06 01:55:57 +02:00
|
|
|
wsr a2, ptevaddr
|
2012-05-27 16:34:54 +02:00
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, TLB_BASE | 7 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
|
2012-05-27 16:34:54 +02:00
|
|
|
movi a4, 0x04000003 | ((\pt_ring) << 4) /* PADDR 64M */
|
|
|
|
|
wdtlb a4, a3
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
movi a3, ((\paddr) & 0xfffff000) | ((\pte_ring) << 4) | (\pte_attr)
|
|
|
|
|
movi a1, ((\vaddr) >> 12) << 2
|
|
|
|
|
add a2, a1, a2
|
|
|
|
|
s32i a3, a2, 0
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, TLB_BASE | 7 | (((\vaddr) >> 10) & 0xfffff000) /* way 7 */
|
2012-05-27 16:34:54 +02:00
|
|
|
movi a4, 0x04000000 | ((\pt_ring) << 4) | (\pt_attr) /* PADDR 64M */
|
|
|
|
|
wdtlb a4, a3
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
movi a3, (\vaddr)
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* out: PS.RING=ring, PS.EXCM=excm, a3=vaddr */
|
|
|
|
|
.macro go_ring ring, excm, vaddr
|
|
|
|
|
movi a3, 10f
|
|
|
|
|
pitlb a3, a3
|
|
|
|
|
ritlb1 a2, a3
|
|
|
|
|
movi a1, 0x10
|
|
|
|
|
or a2, a2, a1
|
|
|
|
|
movi a1, 0x000ff000
|
|
|
|
|
and a3, a3, a1
|
|
|
|
|
movi a1, 4
|
|
|
|
|
or a3, a3, a1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a5, BASE
|
|
|
|
|
add a3, a3, a5
|
2012-05-27 16:34:54 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
movi a3, 10f
|
|
|
|
|
movi a1, 0x000fffff
|
|
|
|
|
and a1, a3, a1
|
2022-04-26 05:05:18 +02:00
|
|
|
add a1, a1, a5
|
2012-05-27 16:34:54 +02:00
|
|
|
|
|
|
|
|
movi a2, 0
|
|
|
|
|
wsr a2, excvaddr
|
|
|
|
|
|
|
|
|
|
movi a3, \vaddr
|
|
|
|
|
movi a2, 0x4000f | ((\ring) << 6) | ((\excm) << 4)
|
|
|
|
|
jx a1
|
|
|
|
|
10:
|
|
|
|
|
wsr a2, ps
|
|
|
|
|
isync
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* in: a3 -- virtual address to test */
|
|
|
|
|
.macro assert_auto_tlb
|
|
|
|
|
movi a2, 0x4000f
|
|
|
|
|
wsr a2, ps
|
|
|
|
|
isync
|
|
|
|
|
pdtlb a2, a3
|
|
|
|
|
movi a1, 0xfffff01f
|
|
|
|
|
and a2, a2, a1
|
|
|
|
|
movi a1, 0xfffff000
|
|
|
|
|
and a1, a1, a3
|
|
|
|
|
xor a1, a1, a2
|
|
|
|
|
assert gei, a1, 0x10
|
|
|
|
|
movi a2, 0x14
|
|
|
|
|
assert lt, a1, a2
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/* in: a3 -- virtual address to test */
|
|
|
|
|
.macro assert_no_auto_tlb
|
|
|
|
|
movi a2, 0x4000f
|
|
|
|
|
wsr a2, ps
|
|
|
|
|
isync
|
2011-09-06 01:55:57 +02:00
|
|
|
pdtlb a2, a3
|
|
|
|
|
movi a1, 0x10
|
|
|
|
|
and a1, a1, a2
|
|
|
|
|
assert eqi, a1, 0
|
2012-05-27 16:34:54 +02:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro assert_sr sr, v
|
|
|
|
|
rsr a2, \sr
|
|
|
|
|
movi a1, (\v)
|
|
|
|
|
assert eq, a1, a2
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro assert_epc1_1m vaddr
|
|
|
|
|
movi a2, (\vaddr)
|
|
|
|
|
movi a1, 0xfffff
|
2011-09-06 01:55:57 +02:00
|
|
|
and a1, a1, a2
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a5, BASE
|
|
|
|
|
add a1, a1, a5
|
2012-05-27 16:34:54 +02:00
|
|
|
rsr a2, epc1
|
|
|
|
|
assert eq, a1, a2
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
test dtlb_autoload
|
|
|
|
|
set_vector kernel, 0
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 0, 3, 1, BASE + 0x1000, 0x1000, 3
|
2012-05-27 16:34:54 +02:00
|
|
|
assert_no_auto_tlb
|
|
|
|
|
|
|
|
|
|
l8ui a1, a3, 0
|
|
|
|
|
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
assert_auto_tlb
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test autoload_load_store_privilege
|
|
|
|
|
set_vector kernel, 0
|
|
|
|
|
set_vector double, 2f
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 0, 3, 0, BASE + 0x2000, 0x2000, 3
|
|
|
|
|
movi a3, BASE + 0x2004
|
2012-05-27 16:34:54 +02:00
|
|
|
assert_no_auto_tlb
|
|
|
|
|
|
|
|
|
|
movi a2, 0x4005f /* ring 1 + excm => cring == 0 */
|
|
|
|
|
wsr a2, ps
|
|
|
|
|
isync
|
|
|
|
|
1:
|
|
|
|
|
l32e a2, a3, -4 /* ring used */
|
|
|
|
|
test_fail
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
addi a1, a3, -4
|
|
|
|
|
assert eq, a1, a2
|
|
|
|
|
|
|
|
|
|
assert_auto_tlb
|
|
|
|
|
assert_sr depc, 1b
|
|
|
|
|
assert_sr exccause, 26
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test autoload_pte_load_prohibited
|
|
|
|
|
set_vector kernel, 2f
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 0, 3, 0, BASE + 0x3000, 0, 0xc
|
2012-05-27 16:34:54 +02:00
|
|
|
assert_no_auto_tlb
|
|
|
|
|
1:
|
|
|
|
|
l32i a2, a3, 0
|
|
|
|
|
test_fail
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
assert_auto_tlb
|
|
|
|
|
assert_sr epc1, 1b
|
|
|
|
|
assert_sr exccause, 28
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test autoload_pt_load_prohibited
|
|
|
|
|
set_vector kernel, 2f
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 0, 0xc, 0, BASE + 0x4000, 0x4000, 3
|
2012-05-27 16:34:54 +02:00
|
|
|
assert_no_auto_tlb
|
|
|
|
|
1:
|
|
|
|
|
l32i a2, a3, 0
|
|
|
|
|
test_fail
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
assert_no_auto_tlb
|
|
|
|
|
assert_sr epc1, 1b
|
|
|
|
|
assert_sr exccause, 24
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test autoload_pt_privilege
|
|
|
|
|
set_vector kernel, 2f
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 0, 3, 1, BASE + 0x5000, 0, 3
|
|
|
|
|
go_ring 1, 0, BASE + 0x5001
|
2012-05-27 16:34:54 +02:00
|
|
|
|
|
|
|
|
l8ui a2, a3, 0
|
|
|
|
|
1:
|
|
|
|
|
syscall
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
assert_auto_tlb
|
|
|
|
|
assert_epc1_1m 1b
|
|
|
|
|
assert_sr exccause, 1
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test autoload_pte_privilege
|
|
|
|
|
set_vector kernel, 2f
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 0, 3, 0, BASE + 0x6000, 0, 3
|
|
|
|
|
go_ring 1, 0, BASE + 0x6001
|
2012-05-27 16:34:54 +02:00
|
|
|
1:
|
|
|
|
|
l8ui a2, a3, 0
|
|
|
|
|
syscall
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
assert_auto_tlb
|
|
|
|
|
assert_epc1_1m 1b
|
|
|
|
|
assert_sr exccause, 26
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test autoload_3_level_pt
|
|
|
|
|
set_vector kernel, 2f
|
2022-04-26 05:05:18 +02:00
|
|
|
pt_setup 1, 3, 1, BASE + 0x00400000, 0, 3
|
|
|
|
|
pt_setup 1, 3, 1, TLB_BASE + ((BASE + 0x00400000) >> 10), 0x2000000, 3
|
|
|
|
|
go_ring 1, 0, BASE + 0x00400001
|
2012-05-27 16:34:54 +02:00
|
|
|
1:
|
|
|
|
|
l8ui a2, a3, 0
|
|
|
|
|
syscall
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, excvaddr
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
assert_no_auto_tlb
|
|
|
|
|
assert_epc1_1m 1b
|
|
|
|
|
assert_sr exccause, 24
|
2011-09-06 01:55:57 +02:00
|
|
|
test_end
|
|
|
|
|
|
2014-05-20 20:24:56 +02:00
|
|
|
test cross_page_insn
|
|
|
|
|
set_vector kernel, 2f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x04000003 /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
wdtlb a2, a3
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007fff
|
2014-05-20 20:24:56 +02:00
|
|
|
movi a3, 20f
|
|
|
|
|
movi a4, 21f
|
|
|
|
|
sub a4, a4, a3
|
|
|
|
|
loop a4, 1f
|
|
|
|
|
l8ui a5, a3, 0
|
|
|
|
|
s8i a5, a2, 0
|
|
|
|
|
addi a2, a2, 1
|
|
|
|
|
addi a3, a3, 1
|
|
|
|
|
1:
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007fff
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: OK, ITLB: OK */
|
|
|
|
|
jx a2
|
|
|
|
|
|
|
|
|
|
.begin no-transform
|
|
|
|
|
20:
|
|
|
|
|
l32i a2, a3, 0
|
|
|
|
|
syscall
|
|
|
|
|
21:
|
|
|
|
|
.end no-transform
|
|
|
|
|
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 1
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x8002
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert ne, a2, a3
|
|
|
|
|
|
|
|
|
|
reset_ps
|
|
|
|
|
set_vector kernel, 3f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x0400000c /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007fff
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: FAIL, ITLB: OK */
|
|
|
|
|
jx a2
|
|
|
|
|
3:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 28
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
reset_ps
|
|
|
|
|
set_vector kernel, 4f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x0400000c /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
movi a2, 0x04000003 /* PPN */
|
|
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007fff
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: OK, ITLB: FAIL */
|
|
|
|
|
jx a2
|
|
|
|
|
4:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 20
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
reset_ps
|
|
|
|
|
set_vector kernel, 5f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x0400000c /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007fff
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: FAIL, ITLB: FAIL */
|
|
|
|
|
jx a2
|
|
|
|
|
5:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 20
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
test_end
|
|
|
|
|
|
|
|
|
|
test cross_page_tb
|
|
|
|
|
set_vector kernel, 2f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x04000003 /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
wdtlb a2, a3
|
|
|
|
|
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
movi a3, 20f
|
|
|
|
|
movi a4, 21f
|
|
|
|
|
sub a4, a4, a3
|
|
|
|
|
loop a4, 1f
|
|
|
|
|
l8ui a5, a3, 0
|
|
|
|
|
s8i a5, a2, 0
|
|
|
|
|
addi a2, a2, 1
|
|
|
|
|
addi a3, a3, 1
|
|
|
|
|
1:
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007ffc
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: OK, ITLB: OK */
|
|
|
|
|
jx a2
|
|
|
|
|
|
|
|
|
|
.begin no-transform
|
|
|
|
|
20:
|
|
|
|
|
l32i a2, a3, 0
|
|
|
|
|
syscall
|
|
|
|
|
21:
|
|
|
|
|
.end no-transform
|
|
|
|
|
|
|
|
|
|
2:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 1
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
assert ne, a2, a3
|
|
|
|
|
|
|
|
|
|
reset_ps
|
|
|
|
|
set_vector kernel, 3f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x0400000c /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007ffc
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: FAIL, ITLB: OK */
|
|
|
|
|
jx a2
|
|
|
|
|
3:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 28
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
|
|
|
|
|
reset_ps
|
|
|
|
|
set_vector kernel, 4f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x0400000c /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
witlb a2, a3
|
|
|
|
|
movi a2, 0x04000003 /* PPN */
|
|
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007ffc
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: OK, ITLB: FAIL */
|
|
|
|
|
jx a2
|
|
|
|
|
4:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 20
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7fff
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
assert ne, a2, a3
|
|
|
|
|
|
|
|
|
|
reset_ps
|
|
|
|
|
set_vector kernel, 5f
|
|
|
|
|
|
|
|
|
|
movi a2, 0x0400000c /* PPN */
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00008000 /* VPN */
|
2014-05-20 20:24:56 +02:00
|
|
|
wdtlb a2, a3
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a2, BASE + 0x00007ffc
|
|
|
|
|
movi a3, BASE + 0x00008000
|
2014-05-20 20:24:56 +02:00
|
|
|
/* DTLB: FAIL, ITLB: FAIL */
|
|
|
|
|
jx a2
|
|
|
|
|
5:
|
|
|
|
|
rsr a2, exccause
|
|
|
|
|
movi a3, 28
|
|
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, epc1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x7ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
rsr a2, excsave1
|
2022-04-26 05:05:18 +02:00
|
|
|
movi a3, BASE + 0x00007ffc
|
2014-05-20 20:24:56 +02:00
|
|
|
assert eq, a2, a3
|
|
|
|
|
test_end
|
|
|
|
|
|
2019-02-18 16:19:02 +01:00
|
|
|
#endif
|
|
|
|
|
|
2011-09-06 01:55:57 +02:00
|
|
|
test_suite_end
|
