322 lines
8.8 KiB
C
322 lines
8.8 KiB
C
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/*
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* ARM Versatile Platform Baseboard System emulation.
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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#include "vl.h"
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#include "arm_pic.h"
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#define KERNEL_ARGS_ADDR 0x100
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#define KERNEL_LOAD_ADDR 0x00010000
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#define INITRD_LOAD_ADDR 0x00800000
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/* Primary interrupt controller. */
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typedef struct vpb_sic_state
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{
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arm_pic_handler handler;
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uint32_t base;
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uint32_t level;
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uint32_t mask;
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uint32_t pic_enable;
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void *parent;
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int irq;
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} vpb_sic_state;
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static void vpb_sic_update(vpb_sic_state *s)
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{
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uint32_t flags;
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flags = s->level & s->mask;
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pic_set_irq_new(s->parent, s->irq, flags != 0);
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}
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static void vpb_sic_update_pic(vpb_sic_state *s)
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{
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int i;
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uint32_t mask;
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for (i = 21; i <= 30; i++) {
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mask = 1u << i;
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if (!(s->pic_enable & mask))
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continue;
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pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
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}
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}
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static void vpb_sic_set_irq(void *opaque, int irq, int level)
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{
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vpb_sic_state *s = (vpb_sic_state *)opaque;
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if (level)
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s->level |= 1u << irq;
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else
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s->level &= ~(1u << irq);
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if (s->pic_enable & (1u << irq))
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pic_set_irq_new(s->parent, irq, level);
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vpb_sic_update(s);
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}
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static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
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{
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vpb_sic_state *s = (vpb_sic_state *)opaque;
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offset -= s->base;
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switch (offset >> 2) {
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case 0: /* STATUS */
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return s->level & s->mask;
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case 1: /* RAWSTAT */
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return s->level;
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case 2: /* ENABLE */
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return s->mask;
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case 4: /* SOFTINT */
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return s->level & 1;
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case 8: /* PICENABLE */
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return s->pic_enable;
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default:
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printf ("vpb_sic_read: Bad register offset 0x%x\n", offset);
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return 0;
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}
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}
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static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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vpb_sic_state *s = (vpb_sic_state *)opaque;
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offset -= s->base;
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switch (offset >> 2) {
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case 2: /* ENSET */
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s->mask |= value;
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break;
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case 3: /* ENCLR */
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s->mask &= ~value;
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break;
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case 4: /* SOFTINTSET */
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if (value)
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s->mask |= 1;
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break;
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case 5: /* SOFTINTCLR */
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if (value)
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s->mask &= ~1u;
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break;
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case 8: /* PICENSET */
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s->pic_enable |= (value & 0x7fe00000);
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vpb_sic_update_pic(s);
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break;
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case 9: /* PICENCLR */
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s->pic_enable &= ~value;
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vpb_sic_update_pic(s);
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break;
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default:
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printf ("vpb_sic_write: Bad register offset 0x%x\n", offset);
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return;
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}
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vpb_sic_update(s);
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}
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static CPUReadMemoryFunc *vpb_sic_readfn[] = {
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vpb_sic_read,
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vpb_sic_read,
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vpb_sic_read
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};
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static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
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vpb_sic_write,
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vpb_sic_write,
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vpb_sic_write
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};
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static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
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{
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vpb_sic_state *s;
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int iomemtype;
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s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
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if (!s)
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return NULL;
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s->handler = vpb_sic_set_irq;
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s->base = base;
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s->parent = parent;
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s->irq = irq;
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iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
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vpb_sic_writefn, s);
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cpu_register_physical_memory(base, 0x00000fff, iomemtype);
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/* ??? Save/restore. */
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return s;
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}
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/* Board init. */
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/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
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static uint32_t bootloader[] = {
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0xe3a00000, /* mov r0, #0 */
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0xe3a01083, /* mov r1, #0x83 */
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0xe3811c01, /* orr r1, r1, #0x100 */
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0xe59f2000, /* ldr r2, [pc, #0] */
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0xe59ff000, /* ldr pc, [pc, #0] */
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0, /* Address of kernel args. Set by integratorcp_init. */
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0 /* Kernel entry point. Set by integratorcp_init. */
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};
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static void set_kernel_args(uint32_t ram_size, int initrd_size,
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const char *kernel_cmdline)
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{
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uint32_t *p;
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p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
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/* ATAG_CORE */
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stl_raw(p++, 5);
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stl_raw(p++, 0x54410001);
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stl_raw(p++, 1);
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stl_raw(p++, 0x1000);
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stl_raw(p++, 0);
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/* ATAG_MEM */
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stl_raw(p++, 4);
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stl_raw(p++, 0x54410002);
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stl_raw(p++, ram_size);
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stl_raw(p++, 0);
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if (initrd_size) {
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/* ATAG_INITRD2 */
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stl_raw(p++, 4);
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stl_raw(p++, 0x54420005);
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stl_raw(p++, INITRD_LOAD_ADDR);
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stl_raw(p++, initrd_size);
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}
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if (kernel_cmdline && *kernel_cmdline) {
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/* ATAG_CMDLINE */
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int cmdline_size;
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cmdline_size = strlen(kernel_cmdline);
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memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
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cmdline_size = (cmdline_size >> 2) + 1;
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stl_raw(p++, cmdline_size + 2);
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stl_raw(p++, 0x54410009);
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p += cmdline_size;
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}
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/* ATAG_END */
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stl_raw(p++, 0);
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stl_raw(p++, 0);
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}
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static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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CPUState *env;
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int kernel_size;
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int initrd_size;
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int n;
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void *pic;
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void *sic;
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env = cpu_init();
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cpu_arm_set_model(env, ARM_CPUID_ARM926);
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/* ??? RAM shoud repeat to fill physical memory space. */
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/* SDRAM at address zero. */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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pic = arm_pic_init_cpu(env);
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pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
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sic = vpb_sic_init(0x10003000, pic, 31);
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pl050_init(0x10006000, sic, 3, 0);
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pl050_init(0x10007000, sic, 4, 1);
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/* TODO: Init PCI NICs. */
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "smc91c111") == 0) {
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smc91c111_init(&nd_table[0], 0x10010000, sic, 25);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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pl011_init(0x101f1000, pic, 12, serial_hds[0]);
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pl011_init(0x101f2000, pic, 13, serial_hds[1]);
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pl011_init(0x101f3000, pic, 14, serial_hds[2]);
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pl011_init(0x10009000, sic, 6, serial_hds[3]);
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pl080_init(0x10130000, pic, 17);
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sp804_init(0x101e2000, pic, 4);
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sp804_init(0x101e3000, pic, 5);
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/* The versatile/PB actually has a modified Color LCD controller
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that includes hardware cursor support from the PL111. */
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pl110_init(ds, 0x10120000, pic, 16, 1);
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/* 0x10000000 System registers. */
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/* 0x10001000 PCI controller config registers. */
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/* 0x10002000 Serial bus interface. */
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/* 0x10003000 Secondary interrupt controller. */
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/* 0x10004000 AACI (audio). */
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/* 0x10005000 MMCI0. */
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/* 0x10006000 KMI0 (keyboard). */
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/* 0x10007000 KMI1 (mouse). */
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/* 0x10008000 Character LCD Interface. */
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/* 0x10009000 UART3. */
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/* 0x1000a000 Smart card 1. */
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/* 0x1000b000 MMCI1. */
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/* 0x10010000 Ethernet. */
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/* 0x10020000 USB. */
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/* 0x10100000 SSMC. */
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/* 0x10110000 MPMC. */
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/* 0x10120000 CLCD Controller. */
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/* 0x10130000 DMA Controller. */
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/* 0x10140000 Vectored interrupt controller. */
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/* 0x101d0000 AHB Monitor Interface. */
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/* 0x101e0000 System Controller. */
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/* 0x101e1000 Watchdog Interface. */
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/* 0x101e2000 Timer 0/1. */
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/* 0x101e3000 Timer 2/3. */
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/* 0x101e4000 GPIO port 0. */
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/* 0x101e5000 GPIO port 1. */
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/* 0x101e6000 GPIO port 2. */
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/* 0x101e7000 GPIO port 3. */
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/* 0x101e8000 RTC. */
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/* 0x101f0000 Smart card 0. */
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/* 0x101f1000 UART0. */
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/* 0x101f2000 UART1. */
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/* 0x101f3000 UART2. */
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/* 0x101f4000 SSPI. */
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/* Load the kernel. */
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if (!kernel_filename) {
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fprintf(stderr, "Kernel image must be specified\n");
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exit(1);
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}
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kernel_size = load_image(kernel_filename,
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phys_ram_base + KERNEL_LOAD_ADDR);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
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exit(1);
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}
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename,
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phys_ram_base + INITRD_LOAD_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initrd '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_size = 0;
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}
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bootloader[5] = KERNEL_ARGS_ADDR;
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bootloader[6] = KERNEL_LOAD_ADDR;
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for (n = 0; n < sizeof(bootloader) / 4; n++)
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stl_raw(phys_ram_base + (n * 4), bootloader[n]);
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set_kernel_args(ram_size, initrd_size, kernel_cmdline);
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}
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QEMUMachine versatilepb_machine = {
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"versatilepb",
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"ARM Versatile/PB (ARM926EJ-S)",
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vpb_init,
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};
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